Datasheet

124
ATmega8A [DATASHEET]
8159E–AVR–02/2013
19.5.2 SPSR – SPI Status Register
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global
interrupts are enabled. If SS
is an input and is driven low when the SPI is in Master mode, this will also set the SPIF
Flag. SPIF is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register
(SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF
bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.
• Bit 5:1 – Res: Reserved Bits
These bits are reserved bits in the ATmega8A and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode
(see Table 19-5). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is config-
ured as Slave, the SPI is only guaranteed to work at f
osc
/4 or lower.
The SPI interface on the ATmega8A is also used for Program memory and EEPROM downloading or uploading.
See page 220 for Serial Programming and verification.
19.5.3 SPDR – SPI Data Register
Table 19-5. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
000
f
osc
/4
001f
osc
/16
010
f
osc
/64
011f
osc
/128
100f
osc
/2
101f
osc
/8
110
f
osc
/32
111f
osc
/64
Bit 76543210
SPIF WCOL – – – – – SPI2X SPSR
Read/WriteRRRRRRRR/W
Initial Value00000000
Bit 76543210
MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X X Undefined