Datasheet

15.9.2 WDTCSR – Watchdog Timer Control Register

Name: WDTCSR

Offset: 0x60 [ID-000004d0]

Reset: 0x00

Bit 7 6 5 4 3 2 1 0

WDIF WDIE WDP[3] WDCE WDE WDP[2:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – WDIF Watchdog Interrupt Flag

This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is configured for

interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, WDIF is cleared by writing a '1' to it. When the I-bit in SREG and WDIE are set, the

Watchdog Timeout Interrupt is executed.

Bit 6 – WDIE Watchdog Interrupt Enable

When this bit is written to '1' and the I-bit in the Status register is set, the Watchdog Interrupt is enabled. If

WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt mode, and the

corresponding interrupt is executed if timeout in the Watchdog Timer occurs. If WDE is set, the Watchdog

Timer is in Interrupt and System Reset mode. The first timeout in the Watchdog Timer will set WDIF.

Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the

Watchdog goes to System Reset mode).

This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and

System Reset mode, WDIE must be set after each interrupt. This should not be done within the interrupt

service routine itself, as this might compromise the safety function of the Watchdog System Reset mode.

If the interrupt is not executed before the next timeout, a System Reset will be applied.

Table 15-1. Watchdog Timer Configuration

WDTON

(1)

WDE WDIE Mode Action on Time-out

1 0 0 Stopped None

1 0 1 Interrupt mode Interrupt

1 1 0 System Reset mode Reset

1 1 1 Interrupt and System Reset mode Interrupt, then go to System Reset mode

0 x x System Reset mode Reset

Note: 1. WDTON Fuse set to '0' means programmed and '1' means unprogrammed.

Bit 5 – WDP[3] Watchdog Timer Prescaler 3

Bit 4 – WDCE Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or

change the prescaler bits, WDCE must be set. Once written to '1', hardware will clear WDCE after four

clock cycles. Refer to 15.8.2 Overview in section Watchdog Timer for information on how to use WDCE.

ATmega48PA/88PA/168PA

System Control and Reset

Datasheet Complete

DS40002011A-page 86