Datasheet
• Watchdog System Reset
• Watchdog Interrupt
• Brown-out Reset
• Two-wire Serial Interface Address Match
• Timer/Counter Interrupt
• SPM/EEPROM Ready Interrupt
• External Level Interrupt on INT
• Pin Change Interrupt
Note: 1. Timer/Counter will only keep running in Asynchronous mode.
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22. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous Operation
14.6 Power-Down Mode
When the SM[2:0] bits are written to '010', the SLEEP instruction makes the MCU enter the Power-Down
mode. In this mode, the external oscillator is stopped, while the external interrupts, the two-wire serial
interface address watch, and the Watchdog continue operating (if enabled).
Only one of these events can wake up the MCU:
• External Reset
• Watchdog System Reset
• Watchdog Interrupt
• Brown-out Reset
• Two-wire Serial Interface Address Match
• External level Interrupt on INT
• Pin Change Interrupt
This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note: If a level triggered interrupt is used for wake-up from power-down, the required level must be held
long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears
before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
start-up time is defined by the SUT and CKSEL Fuses.
When waking up from the Power-Down mode, there is a delay from the wake-up condition occurs until
the wake-up becomes effective. This allows the clock to restart and become stable after having been
stopped. The wake-up period is defined by the same CKSEL fuses that define the Reset time-out period.
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13. System Clock and Clock Options
14.7 Power-Save Mode
When the SM[2:0] bits are written to 011, the SLEEP instruction makes the MCU enter Power-Save
mode. This mode is identical to power-down, except:
If timer/counter2 is enabled, it will keep running during sleep. The device can wake-up from either timer
overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt
enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set.
ATmega48PA/88PA/168PA
Power Management and Sleep Modes
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 70