Datasheet

12.4.2 Preventing EEPROM Corruption

During periods of low V

CC,

the EEPROM data can be corrupted because the supply voltage is too low for

the CPU and the EEPROM to operate properly. These issues are the same as for board level systems

using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular

write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself

can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done

by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not

match the needed detection level, an external low V

Reset protection circuit can be used. If a Reset

occurs while a write operation is in progress, the write operation will be completed provided that the

power supply voltage is sufficient.

12.5 I/O Memory

The I/O space definition of the device is shown in the Register Summary.

All device I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the

LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working

registers and the I/O space. I/O registers within the address range 0x00-0x1F are directly bit-accessible

using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using

the SBIS and SBIC instructions.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00-0x3F must be used. When

addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these

addresses. The device is a complex microcontroller with more peripheral units than can be supported

within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space

from 0x60..0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O

memory addresses should never be written.

Some of the status flags are cleared by writing a '1' to them; this is described in the flag descriptions.

Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and

can, therefore, be used on registers containing such status flags. The CBI and SBI instructions work with

registers 0x00-0x1F only.

The I/O and peripherals control registers are explained in later sections.