Datasheet

12.3.1 Data Memory Access Times
The internal data SRAM access is performed in two clk
CPU
cycles as described in the following Figure.
Figure 12-6. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
12.4 EEPROM Data Memory
The ATmega48PA/88PA/168PA contains 256/512/512B of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address registers, the EEPROM Data
register, and the EEPROM Control register.
See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programming
mode.
Related Links
32. Memory Programming (MEMPROG)
12.4.1 EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 12-2. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write
the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or
fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower
than specified as a minimum for the clock frequency used. Refer to 12.4.2 Preventing EEPROM
Corruption for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to
the description of the EEPROM Control register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction
is executed.
ATmega48PA/88PA/168PA
AVR Memories
© 2018 Microchip Technology Inc.
Datasheet Complete
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