Datasheet

software itself, it is recommended to program the Boot Lock bit11 to protect the boot loader software from
any internal software changes.
31.8.6 Prevent Reading the RWW Section During Self-Programming
During self-programming (either page erase or page write), the RWW section is always blocked for
reading. The user software itself must prevent that this section is addressed during the self-programming
operation. The RWWSB in the SPMCSR (SPMCSR.RWWSB) will be set as long as the RWW section is
busy. During self-programming the interrupt vector table should be moved to the BLS as described in
Watchdog Timer chapter or the interrupts must be disabled. Before addressing the RWW section after the
programming is completed, the user software must clear the SPMCSR.RWWSB by writing the
SPMCSR.RWWSRE. Refer to 30.2.5 Simple Assembly Code Example for a Boot Loader for an example.
Related Links
15.6 Watchdog System Reset
31.8.7 Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write “0x0001001” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Bit 7 6 5 4 3 2 1 0
R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1
The tables in 31.5 Boot Loader Lock Bits show how the different settings of the Boot Loader bits affect
the Flash access.
If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction
is executed within four cycles after BLBSET and SPMEN are set in SPMCSR (SPMCSR.BLBSET and
SPMCSR.SPMEN). For future compatibility, it is recommended to load the Z-pointer with 0x0001 (same
as used for reading the l/O
ck
bits). It is also recommended to set bits 7 and 6 in R0 to “1” when writing the
Lock bits. When programming the Lock bits the entire Flash can be read during the operation.
31.8.8 EEPROM Write Prevents Writing to SPMCSR
An EEPROM write operation will block all software programming to Flash. Reading the fuses and Lock
bits from the software will be prevented during the EEPROM write operation. It is recommended to check
the status bit (EEPE) in the EECR Register (EECR.EEPE) and verify that the bit is cleared before writing
to the SPMCSR register.
31.8.9 Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits (LB) from software. To read the Lock bits, load the Z-
pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR (SPMCSR.BLBSET and
SPMCSR.SPMEN). When an LPM instruction is executed within three CPU cycles after the BLBSET and
SPMEN bits are set in SPMCSR (SPMCSR.BLBSET and SPMCSR.SPMEN), the value of the Lock bits
will be loaded in the destination register. The SPMCSR.BLBSET and SPMCSR.SPMEN will auto-clear
upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or
no SPM instruction is executed within four CPU cycles. When SPMCSR.BLBSET and SPMCSR.SPMEN
are cleared, LPM will work as described in the Instruction set Manual.
Bit 7 6 5 4 3 2 1 0
Rd - - BLB12 BLB11 BLB02 BLB01 LB2 LB1
The algorithm for reading the Fuse Low byte (FLB) is similar to the one described above for reading the
Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN
ATmega48PA/88PA/168PA
Boot Loader Support – Read-While-Write Self-...
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Datasheet Complete
DS40002011A-page 354