Datasheet

and updating the ADC data register. The first conversion must be started by writing a '1' to
ADCSRA.ADSC. In this mode, the ADC will perform successive conversions independently of whether
the ADC Interrupt Flag (ADIF) is cleared or not.
If Auto triggering is enabled, single conversions can be started by writing ADCSRA.ADSC to '1'. ADSC
can also be used to determine if a conversion is in progress. The ADSC bit will be read as '1' during a
conversion, independently of how the conversion was started.
28.4 Prescaling and Conversion Timing
Figure 28-3. ADC Prescaler
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2 CK/4 CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and
200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency
to the ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any
CPU frequency above 100 kHz. The prescaling is selected by the ADC Prescaler Select bits in the ADC
Control and Status Register A (ADCSRA.ADPS). The prescaler starts counting from the moment the ADC
is switched on by writing the ADC Enable bit ADCSRA.ADEN to '1'. The prescaler keeps running for as
long as ADEN=1 and is continuously reset when ADEN=0.
When initiating a single ended conversion by writing a '1' to the ADC Start Conversion bit
(ADCSRA.ADSC), the conversion starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (i.e.,
ADCSRA.ADEN is written to '1') takes 25 ADC clock cycles in order to initialize the analog circuitry.
When the bandgap reference voltage is used as input to the ADC, it will take a certain time for the voltage
to stabilize. If not stabilized, the first value read after the first conversion may be wrong.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and
13.5 ADC clock cycles after the start of a first conversion. When a conversion is complete, the result is
written to the ADC Data Registers (ADCL and ADCH), and the ADC Interrupt Flag (ADCSRA.ADIF) is set.
In Single Conversion mode, ADCSRA.ADSC is cleared simultaneously. The software may then set
ADCSRA.ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
ATmega48PA/88PA/168PA
Analog-to-Digital Converter (ADC)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 317