Datasheet

Figure 28-1. Analog-to-Digital Converter Block Schematic Operation
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC DATA REGISTER
(ADCH/ADCL)
MUX2
ADIE
ADFR
ADSC
ADEN
ADIF
ADIF
MUX1
MUX0
ADPS0
ADPS1
ADPS2
MUX3
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL 1.1V
REFERENCE
MUX DECODER
AVCC
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
REFS0
REFS1
ADLAR
CHANNEL SELECTION
ADC[9:0]
ADC MULTIPLEXER
OUTPUT
AREF
BANDGAP
REFERENCE
PRESCALER
GND
INPUT
MUX
TEMPERATURE
SENSOR
The analog input channel is selected by writing to the MUX bits in the ADC Multiplexer Selection register
ADMUX.MUX[3:0]. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference,
can be selected as single ended inputs to the ADC. The ADC is enabled by writing a '1' to the ADC
Enable bit in the ADC Control and Status Register A (ADCSRA.ADEN). Voltage reference and input
channel selections will not take effect until ADEN is set. The ADC does not consume power when ADEN
is cleared, so it is recommended to switch the ADC OFF before entering the power-saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data registers, ADCH and ADCL. By
default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the
ADC Left Adjust Result bit ADMUX.ADLAR.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH.
Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs
ATmega48PA/88PA/168PA
Analog-to-Digital Converter (ADC)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 315