Datasheet

26.9.6 TWI (Slave) Address Mask Register
Name: TWAMR
Offset: 0xBD
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0
Access
R/W R/W R/W R/W R/W R/W R/W R
Reset 0 0 0 0 0 0 0 0
Bits 1, 2, 3, 4, 5, 6, 7 – TWAM TWI (Slave) Address
The TWAMR can be loaded with a 7-bit slave address mask. Each of the bits in TWAMR can mask
(disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to
one then the address match logic ignores the compare between the incoming address bit and the
corresponding bit in TWAR.
Figure 26-22. TWI Address Match Logic
TWAR0
TWAMR0
Address
Bit 0
Address
Match
Address Bit Comparator 6:1
Address Bit Comparator 0
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 308