Datasheet

STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL

and SDA lines to a high impedance state.

Bit 3 – TWWC TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWDR when TWINT is low. This flag is cleared by

writing the TWDR when TWINT is high.

Bit 2 – TWEN TWI Enable

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the

TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters

and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are

terminated, regardless of any ongoing operation.

Bit 0 – TWIE TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for

as long as the TWINT flag is high.

ATmega48PA/88PA/168PA

Two-Wire Serial Interface (TWI)

Datasheet Complete

DS40002011A-page 307