Datasheet

Figure 26-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter Master Receiver
S = START Rs = REPEATED START P = STOP
Transmitted from master to slave Transmitted from slave to master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
26.8 Multi-Master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one
or more of them. The TWI standard ensures that such situations are handled in such a way that one of
the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An
example of an arbitration situation is depicted below, where two masters are trying to transmit data to a
slave receiver.
Figure 26-20. An Arbitration Example
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLAVE
RECEIVER
Device n
SDA
SCL
........
R1 R2
V
CC
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same slave. In this case,
neither the slave nor any of the masters will know about the bus contention.
• Two or more masters are accessing the same slave with different data or direction bit. In this case,
arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output
a '1' on SDA while another master outputs a zero will lose the arbitration. Losing masters will switch
to not addressed Slave mode or wait until the bus is free and transmit a new START condition,
depending on application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA
bits. Masters trying to output a '1' on SDA while another master outputs a zero will lose the
arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being
addressed by the winning master. If addressed, they will switch to SR or ST mode, depending on
the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed
Slave mode or wait until the bus is free and transmit a new START condition, depending on
application software action.
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 300