Datasheet

Status 0xF8 indicates that no relevant information is available because the TWINT flag is not set. This
occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a two-wire serial bus transfer. A bus error
occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of
such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit.
When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO flag must set and
TWINT must be cleared by writing a logic one to it. This causes the TWI to enter the not addressed Slave
mode and to clear the TWSTO flag (no other bits in TWCRn are affected). The SDA and SCL lines are
released, and no STOP condition is transmitted.
Table 26-7. Miscellaneous States
Status Code
(TWSR)
Prescaler Bits are
0
Status of the Two-Wire Serial
Bus and Two-Wire Serial
Interface Hardware
Application Software Response Next Action Taken by
TWI Hardware
To/From
TWDRn
To TWCRn
STA STO TWINT TWEA
0xF8 No relevant state information
available; TWINT = “0”
No TWDRn
action
No TWCRn action Wait or proceed current
transfer
0x00 Bus error due to an illegal
START or STOP condition
No TWDRn
action
0 1 1 X Only the internal hardware
is affected, no STOP
condition is sent on the
bus. In all cases, the bus is
released and TWSTO is
cleared.
26.7.6 Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action. Consider
for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from master to slave and vice versa. The master must instruct the slave
what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from
the slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The master
must keep control of the bus during all these steps, and the steps should be carried out as an atomical
operation. If this principle is violated in a multi-master system, another master can alter the data pointer in
the EEPROM between steps 2 and 3, and the master will read the wrong data location. Such a change in
transfer direction is accomplished by transmitting a REPEATED START between the transmission of the
address byte and reception of the data. After a REPEATED START, the Master keeps ownership of the
bus. The flow in this transfer is depicted in the following figure:
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 299