Datasheet

It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This
implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and
data packets. In other words; All transmissions must contain the same number of data packets,
otherwise, the result of the arbitration is undefined.
26.5 Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in the following figure. The registers
drawn in a thick line are accessible through the AVR data bus.
Figure 26-9. Overview of the TWI Module
TWI Unit
Address Register
(TWAR)
Address Match Unit
Address Comparator
Control Unit
Control Register
(TWCR)
Status Register
(TWSR)
State Machine and
Status control
SCL
Slew-rate
Control
Spike
Filter
SDA
Control
Spike
Filter
Bit Rate Generator
Bit Rate Register
(TWBR)
Prescaler
Bus Interface Unit
START / STOP
Control
Arbitration detection
Ack
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
26.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-
rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit
removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by
setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The
internal pull-ups can in some systems eliminate the need for external ones.
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 277