Datasheet

Figure 26-4. Address Packet Format
SD A
SCL
ST AR T
1 2 7 8 9
Addr MSB Addr LSB R/W ACK
26.3.4 Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an
acknowledge bit. During a data transfer, the ,master generates the clock and the START and STOP
conditions, while the receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is
signaled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the
SDA line high, a NACK is signaled. When the receiver has received the last byte, or for some reason
cannot receive any more bytes, it should inform the transmitter by sending a NACK after the final byte.
The MSB of the data byte is transmitted first.
Figure 26-5. Data Packet Format
1 2 7 8 9
Data MSB Data LSB ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
SLA+R/W Data Byte
STOP, REPEATED
START or Next
Data Byte
26.3.5 Combining Address and Data Packets Into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets, and a
STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note
that the "Wired-ANDing" of the SCL line can be used to implement handshaking between the master and
the slave. The slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock
speed set up by the master is too fast for the slave, or the slave needs extra time for processing between
the data transmissions. The slave extending the SCL low period will not affect the SCL high period, which
is determined by the master. As a consequence, the slave can reduce the TWI data transfer speed by
prolonging the SCL duty cycle.
The following figure depicts a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the
application software.
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 274