Datasheet

Table 26-1. TWI Terminology

Term Description

Master The device that initiates and terminates a transmission. The master also generates the

SCL clock.

Slave The device addressed by a master.

Transmitter The device placing data on the bus.

Receiver The device reading data from the bus.

This device has one instance of TWI. For this reason, the instance index n is omitted.

The Power Reduction TWI bit in the Power Reduction Register (PRRn.PRTWI) must be written to '0' to

enable the two-wire Serial Interface.

TWI0 is in PRR.

Related Links

14. Power Management and Sleep Modes

26.2.2 Electrical Interconnection

As depicted in the TWI bus definition, both bus lines are connected to the positive supply voltage through

pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This

implements a wired-AND function, which is essential to the operation of the interface. A low level on a

TWI bus line is generated when one or more TWI devices output a zero. A high level is output when all

TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR

devices connected to the TWI bus must be powered in order to allow any bus operation.

The number of devices that can be connected to the bus is only limited by the bus capacitance limit of

400 pF and the 7-bit slave address space. Two different sets of specifications are presented there, one

relevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz.

26.3 Data Transfer and Frame Format

26.3.1 Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the

data line must be stable when the clock line is high. The only exception to this rule is for generating start

and stop conditions.

Figure 26-2. Data Validity

SCL

Data Stable Data Stable

Data Change

ATmega48PA/88PA/168PA

Two-Wire Serial Interface (TWI)

Datasheet Complete

DS40002011A-page 272