Datasheet

24.12.3 USART Control and Status Register 0 B
Name: UCSR0B
Offset: 0xC1
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80
Access
R/W R/W R/W R/W R/W R/W R R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – RXCIE0 RX Complete Interrupt Enable 0
Writing this bit to one enables interrupt on the RXC0 flag. A USART receive complete interrupt will be
generated only if the RXCIE0 bit is written to one, the global interrupt flag in SREG is written to one and
the RXC0 bit in UCSR0A is set.
Bit 6 – TXCIE0 TX Complete Interrupt Enable 0
Writing this bit to one enables interrupt on the TXC0 flag. A USART transmit complete interrupt will be
generated only if the TXCIE0 bit is written to one, the global interrupt flag in SREG is written to one and
the TXC0 bit in UCSR0A is set.
Bit 5 – UDRIE0 USART Data Register Empty Interrupt Enable 0
Writing this bit to one enables interrupt on the UDRE0 Flag. A data register empty interrupt will be
generated only if the UDRIE0 bit is written to one, the global interrupt flag in SREG is written to one and
the UDRE0 bit in UCSR0A is set.
Bit 4 – RXEN0 Receiver Enable 0
Writing this bit to one enables the USART Receiver. The receiver will override normal port operation for
the RxDn pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE0,
DOR0, and UPE0 flags.
Bit 3 – TXEN0 Transmitter Enable 0
Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation
for the TxD0 pin when enabled. The disabling of the transmitter (writing TXEN0 to zero) will not become
effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and
transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer
override the TxD0 port.
Bit 2 – UCSZ02 Character Size 0
The UCSZ02 bits combined with the UCSZ0[1:0] bit in UCSR0C sets the number of data bits (Character
Size) in a frame the receiver and transmitter use.
This bit is reserved in Master SPI Mode (MSPIM).
Bit 1 – RXB80 Receive Data Bit 8 0
RXB80 is the ninth data bit of the received character when operating with serial frames with nine data
bits. Must be read before reading the low bits from UDR0.
This bit is reserved in MSPIM.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 259