Datasheet

transmitted that has not yet been moved into the Shift register. For compatibility with future devices,
always write this bit to zero when writing the UCSRnA register.
When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRnB is written to '1', the USART data
register empty interrupt will be executed as long as UDRE is set (provided that global interrupts are
enabled). UDRE is cleared by writing UDRn. When interrupt-driven data transmission is used, the data
register empty interrupt routine must either write new data to UDRn in order to clear UDRE or disable the
data register empty interrupt - otherwise, a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) flag bit is set when the entire frame in the Transmit Shift register has been
shifted out and there are no new data currently present in the transmit buffer. The TXC flag bit is either
automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a '1'
to its bit location. The TXC flag is useful in half-duplex communication interfaces (like the RS-485
standard), where a transmitting application must enter Receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Complete Interrupt Enable (TXCIE) bit in UCSRnB is written to '1', the USART
transmit complete interrupt will be executed when the TXC flag becomes set (provided that global
interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does
not have to clear the TXC flag, this is done automatically when the interrupt is executed.
24.7.4 Parity Generator
The parity generator calculates the Parity bit for the serial frame data. When Parity bit is enabled
(UCSRnC.UPM[1]=1), the transmitter control logic inserts the Parity bit between the last data bit and the
first stop bit of the frame that is sent.
24.7.5 Disabling the Transmitter
When writing the TX Enable bit in the USART Control and Status Register n B (UCSRnB.TXEN) to zero,
the disabling of the transmitter will not become effective until ongoing and pending transmissions are
completed, i.e., when the Transmit Shift register and Transmit Buffer register do not contain data to be
transmitted. When disabled, the transmitter will no longer override the TxDn pin.
24.8 Data Reception – The USART Receiver
The USART receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRnB Register to '1'.
When the receiver is enabled, the normal pin operation of the RxDn pin is overridden by the USART and
given the function as the receiver’s serial input. The baud rate, mode of operation and frame format must
be set up once before any serial reception can be done. If synchronous operation is used, the clock on
the XCKn pin will be used as transfer clock.
24.8.1 Receiving Frames with 5 to 8 Data Bits
The receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be
sampled at the baud rate or XCKn clock, and shifted into the Receive Shift register until the first stop bit
of a frame is received. A second stop bit will be ignored by the receiver. When the first stop bit is
received, i.e., a complete serial frame is present in the Receive Shift register, the contents of the Shift
register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn
I/O location.
The following code example shows a simple USART receive function based on polling of the Receive
Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data
read from the UDR0 will be masked to zero. The USART 0 has to be initialized before the function can be
used. For the assembly code, the received data will be stored in R16 after the code completes.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 245