Datasheet

The UCPOL bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for
data change. As the above timing diagram shows, when UCPOL is zero, the data will be changed at
rising XCKn edge and sampled at falling XCKn edge. If UCPOL is set, the data will be changed at falling
XCKn edge and sampled at rising XCKn edge.
24.5 Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits),
and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as
valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit, followed by the data bits (from five up to nine data bits in total): first the
least significant data bit, then the next data bits ending with the most significant bit. If enabled, the parity
bit is inserted after the data bits, before the one or two stop bits. When a complete frame is transmitted, it
can be directly followed by a new frame, or the communication line can be set to an idle (high) state. the
figure below illustrates the possible combinations of the frame formats. Bits inside brackets are optional.
Figure 24-4. Frame Formats
10 2 3 4 [5] [6] [7] [8] [P]St
Sp
(St / IDLE)(IDLE)
FRAME
St Start bit, always low.
(n) Data bits (0 to 8).
P Parity bit. Can be odd or even.
Sp Stop bit, always high.
IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high.
The frame format used by the USART is set by:
• Character Size bits (UCSRnC.UCSZn[2:0]) select the number of data bits in the frame.
• Parity Mode bits (UCSRnC.UPMn[1:0]) enable and set the type of parity bit.
• Stop Bit Select bit (UCSRnC.USBSn) select the number of stop bits. The Receiver ignores the
second stop bit.
The receiver and transmitter use the same setting. Note that changing the setting of any of these bits will
corrupt all ongoing communication for both the receiver and transmitter. An FE (Frame Error) will only be
detected in cases where the first stop bit is zero.
24.5.1 Parity Bit Calculation
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of
the exclusive or is inverted. The relation between the parity bit and data bits is as follows:

even
= 
  1
 …  
3
 
2
 
1
 
0
 0
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 241