Datasheet

23. Serial Peripheral Interface (SPI)
23.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
23.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device
and peripheral units, or between several AVR devices.
The USART can be used in Master SPI mode, refer to chapter USART in SPI Mode.
To enable the SPI module, Power Reduction Serial Peripheral Interface bit in the Power Reduction
Register (PRR.PRSPI0) must be written to '0'.
ATmega48PA/88PA/168PA
Serial Peripheral Interface (SPI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 227