Datasheet

22.11.9 General Timer/Counter Control Register

Name: GTCCR

Offset: 0x43

Reset: 0x00

Property: When addressing as I/O register: address offset is 0x23

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0

TSM PSRASY PSRSYNC

Access

R/W R/W R/W

Reset 0 0 0

Bit 7 – TSM Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value

that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler

Reset signals asserted. This ensures that the corresponding timer/counters are halted and can be

configured to the same value without the risk of one of them advancing during configuration. When the

TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the timer/

counters start counting simultaneously.

Bit 1 – PSRASY Prescaler Reset Timer/Counter2

When this bit is one, the timer/counter2 prescaler will be reset. This bit is normally cleared immediately by

hardware. If the bit is written when timer/counter2 is operating in Asynchronous mode, the bit will remain

one until the prescaler has been Reset. The bit will not be cleared by hardware if the TSM bit is set.

Bit 0 – PSRSYNC Prescaler Reset

When this bit is one, timer/counter 0, 1 prescaler will be Reset. This bit is normally cleared immediately by

hardware, except if the TSM bit is set. Note that timer/counter 0, 1 share the same prescaler and a Reset

of this prescaler will affect the mentioned timers.

ATmega48PA/88PA/168PA

8-bit Timer/Counter2 (TC2) with PWM and A...

Datasheet Complete

DS40002011A-page 226