Datasheet

The design of the output compare pin logic allows initialization of the OC2x state before the output is
enabled. Note that some COM2x[1:0] bit settings are reserved for certain modes of operation. See
Register Description.
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19.7 Modes of Operation
22.6.1 Compare Output Mode and Waveform Generation
The waveform generator uses the COM2x[1:0] bits differently in normal, CTC, and PWM modes. For all
modes, setting the COM2x[1:0] = 0 tells the waveform generator that no action on the OC2x register is to
be performed on the next compare match. Refer also to the descriptions of the output modes.
A change of the COM2x[1:0] bits state will have effect at the first compare match after the bits are written.
For non-PWM modes, the action can be forced to have an immediate effect by using the FOC2x strobe
bits.
22.7 Modes of Operation
The mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by
the combination of the Waveform Generation mode (WGM2[2:0]) and Compare Output mode
(COM2x[1:0]) bits. The Compare Output mode bits do not affect the counting sequence, while the
Waveform Generation mode bits do. The COM2x[1:0] bits control whether the PWM output generated
should be inverted or not (inverted or non-inverted PWM). For non-PWM modes, the COM2x[1:0] bits
control whether the output should be set, cleared, or toggled at a compare match (See Compare Match
Output Unit).
For detailed timing information refer to Timer/Counter Timing Diagrams.
22.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM2[2:0] = 0). In this mode, the counting direction
is always up (incrementing), and no counter clear is performed. The counter simply overruns when it
passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal
operation, the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the
TCNT2 becomes zero. The TOV2 flag, in this case, behaves like a ninth bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 flag, the
timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using the output
compare to generate waveforms in Normal mode is not recommended since this will occupy too much of
the CPU time.
22.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM2[2:0] = 2), the OCR2A Register is used to manipulate
the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2)
matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the operation of
counting external events.
The timing diagram for the CTC mode is as follows. The counter value (TCNT2) increases until a
compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared.
ATmega48PA/88PA/168PA
8-bit Timer/Counter2 (TC2) with PWM and A...
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Datasheet Complete
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