Datasheet

Figure 20-13. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Note: The “n” in the register and bit names indicates the device number (n = 1 for timer/counter 1), and
the “x” indicates output compare unit (A/B).
20.15 Register Description
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
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Datasheet Complete
DS40002011A-page 182