Datasheet

In Phase Correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Writing COM1x[1:0] bits to 0x2 will produce a non-inverted PWM. An inverted PWM output can be
generated by writing the COM1x[1:0] to 0x3. The actual OC1x value will only be visible on the port pin if
the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by
setting (or clearing) the OC1x register at the compare match between OCR1x and TCNT1 when the
counter increments, and clearing (or setting) the OC1x register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using Phase Correct
PWM can be calculated by the following equation:

OCnxPCPWM
=

clk_I/O
2    TOP
N represents the prescale divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x represent special cases when generating a PWM waveform output in
the Phase Correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low
and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted
PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value
(WGM1[3:0]=0xB) and COM1A[1:0]=0x1, the OC1A output will toggle with a 50% duty cycle.
20.12.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode
(WGM1[3:0] = 0x8 or 0x9) provides a high-resolution phase and frequency correct PWM waveform
generation option. The phase and frequency correct PWM mode are, like the phase correct PWM mode,
based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and
then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is
cleared on the compare match between TCNT1 and OCR1x while up-counting, and set on the compare
match while down-counting. In inverting Compare Output mode, the operation is inverted. The dual-slope
operation gives a lower maximum operation frequency compared to the single-slope operation. However,
due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the
time the OCR1x is updated by the OCR1x Buffer register, (see Figure 20-8 and the Timing Diagram
below).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum
resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the
following equation:

PFCPWM
=
log TOP+1
log 2
In phase and frequency correct PWM mode the counter is incremented until the counter value matches
either the value in ICR1 (WGM1[3:0]=0x8), or the value in OCR1A (WGM1[3:0]=0x9). The counter has
then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one
timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown
below. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to
define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks
on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag
will be set when a compare match occurs.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 178