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20.14 Timer/Counter Timing Diagrams
20.11 Compare Match Output Unit
20.12.1 Normal Mode
The simplest mode of operation is the Normal mode (TCCR1A.WGM1[3:0]=0x0). In this mode, the
counting direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX=0xFFFF) and then restarts from
BOTTOM=0x0000. In normal operation, the Timer/Counter Overflow Flag (TIFR1.TOV) will be set in the
same timer clock cycle as the TCNT1 becomes zero. In this case, the TOV flag in behaves like a 17th bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that
automatically clears the TOV flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written any time.
The input capture unit is easy to use in Normal mode. However, observe that the maximum interval
between the external events must not exceed the resolution of the counter. If the interval between events
are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the
capture unit.
The output compare units can be used to generate interrupts at some given time. Using the output
compare to generate waveforms in Normal mode is not recommended since this will occupy too much of
the CPU time.
20.12.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare (CTC) modes (mode 4 or 12, WGM1[3:0]=0x4 or 0xC), the OCR1A or ICR1
registers are used to manipulate the counter resolution: the counter is cleared to ZERO when the counter
value (TCNT1) matches either the OCR1A (if WGM1[3:0]=0x4) or the ICR1 (WGM1[3:0]=0xC). The
OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater
control of the compare match output frequency. It simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown below. The counter value (TCNT1) increases until a
compare match occurs with either OCR1A or ICR1, and then TCNT1 is cleared.
Figure 20-6. CTC Mode, Timing Diagram
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 4
Period
2 3
(COMnA[1:0] = 0x1)
Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and
the “x” indicates output compare unit (A/B).
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 173