Datasheet

Figure 20-3. Input Capture Unit Block Diagram for TC1

ICFn (Int.Req.)

Analog

Comparator

WRITE

ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

ACIC ICNC ICES

ACO

Note: The “n” in the register and bit names indicates the device number (n = 1 for timer/counter 1), and

the “x” indicates output compare unit (A/B).

When a change of the logic level (an event) occurs on the input capture pin (ICP1), or alternatively on the

Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture

will be triggered: the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1).

The Input Capture Flag (ICF) is set at the same system clock cycle as the TCNT1 value is copied into the

ICR1 . If enabled (TIMSK1.ICIE=1), the ICF generates an input capture interrupt. The ICF1 is

automatically cleared when the interrupt is executed. Alternatively, the ICF can be cleared by software by

writing '1' to its I/O bit location.

Reading the 16-bit value in the ICR1 is done by first reading the low byte (ICR1L) and then the high byte

(ICR1H). When the low byte is read form ICR1L, the high byte is copied into the high byte temporary

The ICR1 can only be written when using a Waveform Generation mode that utilizes the ICR1 for defining

the counter’s TOP value. In these cases the Waveform Generation Mode bits (WGM1[3:0]) must be set

before the TOP value can be written to the ICR1. When writing the ICR1, the high byte must be written to

the ICR1H I/O location before the low byte is written to ICR1L.