Datasheet

Figure 19-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with
Prescaler (f
clk_I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Note: The “n” in the register and bit names indicates the device number (n = 0 for timer/counter 0), and
the “x” indicates output compare unit (A/B).
19.9 Register Description
ATmega48PA/88PA/168PA
8-bit Timer/Counter0 (TC0) with PWM
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Datasheet Complete
DS40002011A-page 149