Datasheet

An interrupt can be generated each time the counter value reaches the TOP value by setting the OCF0A
flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care,
since the CTC mode does not provide double buffering. If the new value written to OCR0A is lower than
the current value of TCNT0, the counter will miss the compare match. The counter will then count to its
maximum value (0xFF for an 8-bit counter, 0xFFFF for a 16-bit counter) and wrap around starting at 0x00
before the compare match will occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on
each compare match by writing the two least significant Compare Output mode bits in the Timer/Counter
Control Register A Control to toggle mode (TCCR0A.COM0A[1:0]=0x1). The OC0A value will only be
visible on the port pin unless the data direction for the pin is set to output. The waveform generated will
have a maximum frequency of f
OC0
= f
clk_I/O
/2 when OCR0A is written to 0x00. The waveform frequency
is defined by the following equation:

OCnx
=

clk_I/O
2   
1 + OCRnx
N represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the Timer/Counter Overflow flag TOV0 is set in the same clock
cycle that the counter wraps from MAX to 0x00.
19.7.3 Fast PWM Mode
The Fast Pulse Width Modulation or Fast PWM modes (WGM0[2:0]=0x3 or WGM0[2:0]=0x7) provide a
high-frequency PWM waveform generation option. The Fast PWM modes differ from the other PWM
options by their single-slope operation. The counter counts from BOTTOM to TOP and then restarts from
BOTTOM. TOP is defined as 0xFF when WGM0[2:0]=0x3. TOP is defined as OCR0A when
WGM0[2:0]=0x7.
In non-inverting Compare Output mode, the Output Compare register (OC0x) is cleared on the compare
match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output
is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating
frequency of the Fast PWM mode can be twice as high as the phase correct PWM modes, which use
dual-slope operation. This high frequency makes the Fast PWM mode well suited for power regulation,
rectification, and DAC applications. High frequency allows physically small sized external components
(coils, capacitors), and therefore reduces total system cost.
In Fast PWM mode, the counter is incremented until the counter value matches the TOP value. The
counter is then cleared at the following timer clock cycle. The timing diagram for the Fast PWM mode is
shown below. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-
slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines
on the TCNT0 slopes mark compare matches between OCR0x and TCNT0.
ATmega48PA/88PA/168PA
8-bit Timer/Counter0 (TC0) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 144