Datasheet

261
ATmega8535(L)
2502K–AVR–10/06
SPI Timing
Characteristics
See Figure 128 and Figure 129 for details.
Table 113. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 59
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5Hold Master 10
6 Out to SCK Master 5 • t
SCK
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • t
ck
11 SCK high/low Slave 2 • t
ck
12 Rise/Fall time Slave 1.6 ns
13 Setup Slave 10
ns
14 Hold Slave 10
15 SCK to out Slave 15
16 SCK to SS
high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 2 • t
ck