Datasheet

130
ATmega8535(L)
2502K–AVR–10/06
Table 54 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase
correct PWM mode.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the
Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct
PWM Mode” on page 125 for more details.
• Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
Table 55.
Timer/Counter Register –
TCNT2
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)
the Compare Match on the following timer clock. Modifying the counter (TCNT2) while
the counter is running, introduces a risk of missing a Compare Match between TCNT2
and the OCR2 Register.
Table 54. Compare Output Mode, Phase Correct PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
01Reserved
1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare
Match when down-counting.
1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare
Match when down-counting.
Table 55. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
T2S
/(No prescaling)
010
clk
T2S
/8 (From prescaler)
011
clk
T2S
/32 (From prescaler)
100
clk
T2S
/64 (From prescaler)
101
clk
T2S
/128 (From prescaler)
110clk
T
2
S
/256 (From prescaler)
111clk
T
2
S
/1024 (From prescaler)
Bit 76543210
TCNT2[7:0] TCNT2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000