Datasheet

115

ATmega8535(L)

2502K–AVR–10/06

Timer/Counter Interrupt Mask

(1)

Note: 1. This register contains interrupt control bits for several Timer/Counters, but only

Timer1 bits are described in this section. The remaining bits are described in their

respective timer sections.

• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The

corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the ICF1

Flag, located in TIFR, is set.

• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 output compare A match interrupt is enabled. The

corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the

OCF1A Flag, located in TIFR, is set.

• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 output compare B match interrupt is enabled. The

corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the

OCF1B Flag, located in TIFR, is set.

• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 46) is executed when the TOV1 Flag, located

in TIFR, is set.

Bit 76543210

OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0