Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming b
Pin Configurations Figure 1.
ATmega8535(L) Overview The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega8535(L) Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.
Resources 6 A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
ATmega8535(L) About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details.
AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
ATmega8535(L) Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-registers, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will, in many cases, remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
ATmega8535(L) General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
ATmega8535(L) Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 224. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
ATmega8535(L) When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
AVR ATmega8535 Memories This section describes the different memories in the ATmega8535. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8535 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega8535 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega8535(L) SRAM Data Memory Figure 9 shows how the ATmega8535 SRAM Memory is organized. The 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 512 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction EEPROM Data Memory Next Instruction The ATmega8535 contains 512 bytes of data EEPROM memory.
ATmega8535(L) The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. • Bits 8..0 – EEAR8..
value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6.
ATmega8535(L) The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega8535(L) EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used.
System Clock and Clock Options Clock Systems and their Distribution Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 32. The clock systems are detailed below. Figure 11.
ATmega8535(L) Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
This mode has a limited frequency range and it can not be used to drive other clock buffers. For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
ATmega8535(L) The CKSEL0 fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.
Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be connected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36 pF.
ATmega8535(L) Table 7. External RC Oscillator Operating Modes CKSEL3..0 Frequency Range (MHz) 0101 0.1 - 0.9 0110 0.9 - 3.0 0111 3.0 - 8.0 1000 8.0 - 12.0 When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 8. Table 8. Start-up Times for the External RC Oscillator Clock Selection SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) 00 18 CK – 01 18 CK 4.
Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK – 01 6 CK 4.1 ms Fast rising power 10(1) 6 CK 65 ms Slowly rising power 11 Note: Oscillator Calibration Register – OSCCAL Recommended Usage BOD enabled Reserved 1. The device is shipped with this option selected.
ATmega8535(L) External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND. Figure 14. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12. Table 12.
Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
ATmega8535(L) Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Twowire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules, including Timer/Counter2 if clocked asynchronously. Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running.
ATmega8535(L) Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega8535(L) Figure 15. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Control and Status Register (MCUCSR) Power-on Reset Circuit Brown-out Reset Circuit BODEN BODLEVEL Pull-up Resistor Spike Filter Reset Circuit Watchdog Timer Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 15. Reset Characteristics Symbol VPOT Typ(1) Max(1) Units Power-on Reset Threshold Voltage (rising) 1.4 2.3 V Power-on Reset Threshold Voltage (falling)(2) 1.3 2.3 V 0.
3. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8535L and BODLEVEL = 0 for ATmega8535. BODLEVEL = 1 is not applicable for ATmega8535.
ATmega8535(L) External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired. Figure 18.
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 41 for details on operation of the Watchdog Timer. Figure 20. Watchdog Reset During Operation CC CK MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
ATmega8535(L) Internal Voltage Reference ATmega8535 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 16.
Table 17. WDT Configuration as a Function of the Fuse Settings of S8538C and WDTON Safety Level WDT Initial State How to Disable the WDT How to Change Time-out S8535C WDTON Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed sequence Unprogrammed Programmed 2 Enabled Always enabled Timed sequence Programmed Unprogrammed 0 Disabled Timed sequence No restriction Programmed Programmed 2 Enabled Always enabled Timed sequence Figure 21.
ATmega8535(L) if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above.
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega8535(L) Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing the Watchdog Timer configuration differs slightly between the three safety levels. Separate procedures are described for each level. Safety Level 0 This mode is compatible with the Watchdog operation found in AT90S8535. The Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
Interrupts Interrupt Vectors in ATmega8535 This section describes the specifics of the interrupt handling as performed in ATmega8535. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 19. Reset and Interrupt Vectors Vector No.
ATmega8535(L) Table 20. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL 1 Note: Reset Address Interrupt Vectors Start Address 0 0x0000 0x0001 1 1 0x0000 Boot Reset Address + 0x0001 0 0 Boot Reset Address 0x0001 0 1 Boot Reset Address Boot Reset Address + 0x0001 1. The Boot Reset Address is shown in Table 93 on page 235. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
AddressLabels Code Comments 0x000 RESET: ldi r16,high(RAMEND) ; Main program start 0x001 out SPH,r16 0x002 ldi r16,low(RAMEND) 0x003 out SPL,r16 0x004 sei 0x005 xxx ; Set Stack Pointer to top of RAM ; Enable interrupts ; .org 0xC01 0xC01 rjmp EXT_INT0 ; IRQ0 Handler 0xC02 rjmp EXT_INT1 ; IRQ1 Handler ... .... 0xC14 ..
ATmega8535(L) Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit 7 6 5 4 3 2 1 0 INT1 INT0 INT2 – – – IVSEL IVCE Read/Write R/W R/W R/W R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GICR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
Assembly Code Example Move_interrupts: ; Enable change of interrupt vectors ldi r16, (1<
ATmega8535(L) I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 23.
ATmega8535(L) 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem.
ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 25.
ATmega8535(L) The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
ATmega8535(L) Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 26 shows how the port pin control signals from the simplified Figure 23 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 26.
Table 22 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 22. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega8535(L) Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 52 for more details about this feature.
Table 25. Overriding Signals for Alternate Functions in PA3..PA0 Alternate Functions Of Port B Signal Name PA3/ADC3 PA2/ADC2 PA1/ADC1 PA0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT The Port B pins with alternate functions are shown in Table 26. Table 26.
ATmega8535(L) • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. • SS – Port B, Bit 4 SS: Slave Select input.
Table 27. Overriding Signals for Alternate Functions in PB7..
ATmega8535(L) TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin.
Table 31. Overriding Signals for Alternate Functions in PC1..PC0(1) Signal Name PC1/SDA PC0/SCL PUOE TWEN TWEN PUOV PORTC1 • PUD PORTC0 • PUD DDOE TWEN TWEN DDOV SDA_OUT SCL_OUT PVOE TWEN TWEN PVOV 0 0 DIEOE 0 0 DIEOV 0 0 DI – – AIO SDA INPUT SCL INPUT Note: Alternate Functions of Port D 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins PC0 and PC1. This is not shown in the figure.
ATmega8535(L) (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. • OC1B – Port D, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDD4 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.
Table 34. Overriding Signals for Alternate Functions in PD3..
ATmega8535(L) Port B Input Pins Address – PINB Bit 7 6 5 4 3 2 1 0 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINB Port C Data Register – PORTC Bit Port C Data Direction Register – DDRC Port C Input Pins Address – PINC 7 6 5 4 3 2 1 0 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0
External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt).
ATmega8535(L) The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 36. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU General Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.
ATmega8535(L) 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27.
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0). See “Output Compare Unit” on page 73. for details. The Compare Match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request.
ATmega8535(L) top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.
The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega8535(L) Compare Match Output Unit The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 30 shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega8535(L) when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.
Figure 32. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin.
ATmega8535(L) Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while up-counting, and set on the Compare Match while down-counting.
OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N ⋅ 510 The “N” variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega8535(L) Figure 35. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 36 shows the setting of OCF0 in all modes except CTC mode. Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
Figure 37.
ATmega8535(L) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 40 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 40. Compare Output Mode, non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected.
ATmega8535(L) • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 43. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/counter stopped). 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).
ATmega8535(L) Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
ATmega8535(L) 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
Figure 40. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
ATmega8535(L) Waveform Generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 98. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 203.
Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega8535(L) The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega8535(L) Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 87. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 101. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
ATmega8535(L) byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register.
measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an output compare interrupt.
ATmega8535(L) sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not the case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
Compare Match Output Unit The Compare Output Mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega8535(L) A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits.
Figure 45. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega8535(L) High frequency allows physically small sized external components (coils, capacitors), hence reducing total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP.
ATmega8535(L) OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution can be calculated in bits by using the following equation: log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) In phase correct PWM mode, the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running.
ATmega8535(L) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown in Figure 48.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 47 on page 111). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x).
ATmega8535(L) Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode, the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 52.
ATmega8535(L) Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 46. Compare Output Mode, Fast PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation OC1A/OC1B disconnected.
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 48. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. See “Modes of Operation” on page 101. Table 48.
ATmega8535(L) Timer/Counter1 Control Register B – TCCR1B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered.
Timer/Counter1 – TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
ATmega8535(L) Timer/Counter Interrupt Mask Register – TIMSK(1) Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIMSK 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
Timer/Counter Interrupt Flag Register – TIFR(1) Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIFR 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
ATmega8535(L) 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
ATmega8535(L) Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 54 shows a block diagram of the counter and its surrounding environment. Figure 54. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement.
Figure 55. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the pulse width modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence.
ATmega8535(L) Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The Waveform Generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 56 shows a simplified schematic of the logic affected by the COM21:0 bit setting.
A change of the COM21:0 bits state will take effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have an immediate effect by using the FOC2 strobe bits. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits.
ATmega8535(L) An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
Figure 58. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
ATmega8535(L) Phase Correct PWM Mode The Phase Correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while up-counting, and set on the Compare Match while down-counting.
between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N ⋅ 510 The “N” variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega8535(L) Figure 61. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 62 shows the setting of OCF2 in all modes except CTC mode. Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
Figure 63.
ATmega8535(L) Table 51. Waveform Generation Mode Bit Description(1) Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation TOP Update of OCR2 TOV2 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
Table 54 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 54. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when down-counting. 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when down-counting. Note: Description 1.
ATmega8535(L) Output Compare Register – OCR2 Bit 7 6 5 4 3 2 1 0 OCR2[7:0] OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.
Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2, and TCCR2. 4.
ATmega8535(L) down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake-up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register 2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega8535(L) Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect.
Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8535 and peripheral devices or between several AVR devices.
ATmega8535(L) done, writing a byte to the SPI Data Register starts the SPI Clock Generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line.
Table 56. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See “Alternate Functions Of Port B” on page 60 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
ATmega8535(L) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega8535(L) SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL functionality is summarized below: Table 57.
ATmega8535(L) SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 57 and Table 58, as done below: Table 60.
ATmega8535(L) USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode.
ATmega8535(L) Figure 70. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
Table 61.
ATmega8535(L) Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 71.
Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.
ATmega8535(L) The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers.
Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock.
ATmega8535(L) Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) Flag bit is set to one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
ATmega8535(L) Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as a transfer clock.
Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR, and PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change.
ATmega8535(L) Note: 1. See “About Code Examples” on page 7. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer.
stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a Parity Error. The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate.
ATmega8535(L) Figure 73. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
Figure 75. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting.
ATmega8535(L) Table 62. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11 -5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 63.
Multi-processor Communication Mode Setting the Multi-processor Communication Mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
ATmega8535(L) Accessing UBRRH/UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents.
ATmega8535(L) For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the transmit Shift Register when the Shift Register is empty.
• Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. • Bit 0 – MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode.
ATmega8535(L) TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. USART Control and Status Register C – UCSRC(1) Bit 7 6 5 4 3 2 1 0 URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 0 0 0 0 1 1 0 Note: UCSRC 1. The UCSRC Register shares the same I/O location as the UBRRH Register.
• Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set. Table 65.
ATmega8535(L) This bit is used for Synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 68.
Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 69. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega8535(L) Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.
Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.
ATmega8535(L) Table 72. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.
Two-wire Serial Interface Features • • • • • • • • • • Two-wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
ATmega8535(L) Electrical Interconnection As depicted in Figure 76, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
Figure 78. START, REPEATED START, and STOP Conditions SDA SCL START Address Packet Format REPEATED START STOP START STOP All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
ATmega8535(L) Figure 80. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA From Transmitter SDA From Receiver SCL From Master 1 2 7 SLA+R/W Combining Address and Data Packets into a Transmission STOP, REPEATED START or Next Data Byte Data Byte A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition is illegal.
period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively. Figure 82.
ATmega8535(L) Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets.
Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.
ATmega8535(L) • After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed by own Slave address or general call. • After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition.
By writing the TWEA bit to zero, the device can be virtually disconnected from the Twowire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. • Bit 5 – TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the Two-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free.
ATmega8535(L) TWI Status Register – TWSR Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 Read/Write R R R R R R R/W R/W Initial Value 1 1 1 1 1 0 0 0 TWSR • Bits 7..3 – TWS: TWI Status These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value.
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 0 The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address (0x00).
ATmega8535(L) Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
ATmega8535(L) In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files.
Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST), and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
ATmega8535(L) Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 86). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition.
ATmega8535(L) Figure 87.
Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (see Figure 88). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
ATmega8535(L) A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 1 X 1 0 X 1 0 X After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 76.
Figure 89.
ATmega8535(L) To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 Value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
Table 77.
ATmega8535(L) Figure 91. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 92). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 92. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER Device 3 MASTER RECEIVER ........
ATmega8535(L) by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source.
Figure 93. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
ATmega8535(L) Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2. The EEPROM must be instructed what location should be read. 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa.
Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits.
ATmega8535(L) Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 41.
ATmega8535(L) Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..
Analog-to-Digital Converter Features • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x(1) Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
ATmega8535(L) Figure 98. Analog-to-Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 0 TRIGGER SELECT ADC[9:0] ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX3 MUX2 MUX4 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS AVCC PRESCALER START GAIN SELECTION CHANNEL SELECTION MUX DECODER CONVERSION LOGIC INTERNAL 2.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL.
ATmega8535(L) Figure 99. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
ATmega8535(L) Figure 102. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 9 Next Conversion 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 103.
Table 82. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 14.5 25 Normal conversions, single ended 1.5 13 Condition Auto Triggered conversions Normal conversions, differential Note: Differential Gain Channels 2 13.5 (1) 1.5/2.5 13/14(1) 1. Depending on the state of CKADC2. When using differential gain channels, certain aspects of the conversion need to be taken into consideration.
ATmega8535(L) If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1. When ADATE or ADEN is cleared. 2. During conversion, minimum one ADC clock cycle after the trigger event. 3. After a conversion, before the interrupt flag used as trigger source is cleared.
If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 114 on page 263 and Table 115 on page 264. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1.
ATmega8535(L) Figure 105. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible.
Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB.
ATmega8535(L) • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 109. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 84 on page 219 and Table 85 on page 220). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega8535(L) Table 83. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + (511/512) VREF/GAIN 0x1FF 511 VADCm + (510/512) VREF/GAIN 0x1FE 510 ... ... VADCm + (1/512) VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - (1/512) VREF/GAIN 0x3FF -1 ... ... VADCm - (511/512) VREF/GAIN 0x201 -511 VADCm - VREF/GAIN 0x200 -512 ... ... Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 85 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 85. Input Channel and Gain Selections MUX4..
ATmega8535(L) Table 85. Input Channel and Gain Selections (Continued) MUX4..0 Single Ended Input 11101 ADC Control and Status Register A – ADCSRA 11110 1.22V (VBG) 11111 0V (GND) Bit Pos Differential Input Neg Differential Input Gain ADC5 ADC2 1x N/A 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC.
Table 86.
ATmega8535(L) Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 7:5 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect.
Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega8535(L) Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write Section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
Figure 113.
ATmega8535(L) Table 89. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Store Program Memory Control Register – SPMCR The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. Bit 7 6 5 4 3 2 1 0 SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN Read/Write R/W R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCR • Bit 7 – SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled.
ATmega8535(L) the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. • Bit 0 – SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles.
Figure 114. Addressing the Flash during SPM(1) BIT 15 ZPCMSB ZPAGEMSB 1 0 Z - REGISTER 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: Self-Programming the Flash 1. The different variables used+ in Figure 114 are listed in Table 95 on page 236. 2. PCPAGE and PCWORD are listed in Table 104 on page 241.
ATmega8535(L) Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega8535(L) Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied.
; re-enable the RWW section ldi spmcrval, (1<
ATmega8535(L) in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out SPMCR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret ATmega8535 Boot Loader Parameters In Table 93 through Table 95, the parameters used in the description of the self programming are given. Table 93.
Table 95. Explanation of Different Variables used in Figure 114 and the Mapping to the Z-pointer(1) Corresponding Z-value Variable PCMSB 11 Most significant bit in the Program Counter. (The Program Counter is 12 bits PC[11:0]) 4 Most significant bit which is used to address the words within one page (64 words in a page requires five bits PC [4:0]). PAGEMSB Z12 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
ATmega8535(L) Memory Programming Program And Data Memory Lock Bits The ATmega8535 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 97. The Lock bits can only be erased to “1” with the Chip Erase command. Table 96.
Table 97. Lock Bit Protection Modes(2) (Continued) Memory Lock Bits 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If interrupt vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
ATmega8535(L) Table 99.
Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8535. Pulses are assumed to be at least 250 ns unless otherwise noted. Signal Names In this section, some pins of the ATmega8535 are referenced by signal names describing their functionality during parallel programming, see Figure 115 and Table 100.
ATmega8535(L) Table 101. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 102. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) 0 1 Load Data (High or Low data byte for Flash determined by BS1) 1 0 Load Command 1 1 No Action, Idle Table 103.
Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100 µs. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 101 on page 241 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering Programming mode.
ATmega8535(L) Programming the Flash The Flash is organized in pages, see Table 104 on page 241. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4.
3. Wait until RDY/BSY goes high. (See Figure 117 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 116.
ATmega8535(L) Programming the EEPROM The EEPROM is organized in pages, see Table 105 on page 241. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 243 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 243 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”.
ATmega8535(L) Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 243 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase.
Parallel Programming Characteristics Figure 121. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 122.
ATmega8535(L) Figure 123. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (low byte) DATA (low byte) DATA (high byte) ADDR1 (low byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 121 (i.e. tDVXH, tXHXL, and tXLDX) also apply to reading operation.
Table 106. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
ATmega8535(L) Serial Downloading Serial Programming Pin Mapping Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 107 on page 251, the pin mapping for SPI programming is listed.
Serial Programming Algorithm When writing serial data to the ATmega8535, data is clocked on the rising edge of SCK. When reading data from the ATmega8535, data is clocked on the falling edge of SCK. See Figure 125 for timing details. To program and verify the ATmega8535 in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 109): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
ATmega8535(L) Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
Table 109. Serial Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction Format Instruction Programming Enable Chip Erase Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
ATmega8535(L) Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40°C to 85°C, VCC = 2.7V to 5.
ATmega8535(L) If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V.
External Clock Drive Waveforms Figure 126. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 110. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 μs tCHCL Fall Time 1.6 0.
ATmega8535(L) Two-wire Serial Interface Characteristics Table 112 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8535 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 127. Table 112. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) (1) VOL tr (1) (1) tof Min Max Units Input Low Voltage -0.5 0.3 VCC V Input High Voltage 0.7 VCC VCC + 0.5 V – V 0.4 V 20 + 0.
4. fCK = CPU clock frequency. 5. This requirement applies to all ATmega8535 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz. 7.
ATmega8535(L) SPI Timing Characteristics See Figure 128 and Figure 129 for details. Table 113. SPI Timing Parameters Description Mode Min Typ 1 SCK period Master See Table 59 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.
Figure 128. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 129. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) 262 MSB ...
ATmega8535(L) ADC Characteristics Table 114. ADC Characteristics, Single Ended Channels Symbol Typ(1) Max(1) Condition Resolution Single Ended Conversion 10 Bits Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz 1.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Noise Reduction mode 1.
Table 115. ADC Characteristics, Differential Channels Symbol Parameter Max(1) Units 1x 10 Bits Gain = 10x 10 Bits Gain = 200x 10 Bits Condition Gain = Resolution Absolute Accuracy Integral Non-Linearity (INL) (Accuracy after Calibration for Offset and Gain Error) Offset Error 18 LSB Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 18 LSB Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 6 LSB Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 0.
ATmega8535(L) Table 115. ADC Characteristics, Differential Channels (Continued) Symbol Parameter Condition Min(1) Typ(1) Max(1) Units 2.3 2.56 2.7 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Notes: 1. Values are guidelines only. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V.
ATmega8535 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega8535(L) Figure 131. Active Supply Current vs. Frequency (1 - 16 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 16 MHz 25 5.5V 5.0V 20 4.5V 15 ICC (mA) 4.0V 10 3.3V 3.0V 5 2.7V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 132. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 18 ICC (mA) 16 -40°C 14 25°C 12 85°C 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
Figure 133. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 10 9 -40°C 8 25°C 85°C ICC (mA) 7 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 134. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 4.5 4 -40°C 25°C 3.5 85°C ICC (mA) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Figure 135. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 2.5 -40°C 2 25°C 85°C ICC (mA) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 136. Active Supply Current vs. VCC (32 kHz External Oscillator) ACTIVE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 0.08 0.07 25°C 0.06 ICC (mA) 0.05 0.04 0.03 0.02 0.01 0 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 137. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.8 5.5V 0.7 5.0V 0.6 4.5V ICC (mA) 0.5 4.0V 0.4 3.3V 0.3 3.0V 2.7V 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 138. Idle Supply Current vs. Frequency (1 - 16 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 16 MHz 14 12 5.5V 5.0V ICC (mA) 10 4.5V 8 6 4.0V 4 3.3V 3.0V 2 2.
ATmega8535(L) Figure 139. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 10 9 -40°C 25°C 85°C 8 7 ICC (mA) 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 140. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 5 4.5 -40°C 25°C 85°C 4 3.5 ICC (mA) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 141. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 2.5 2 -40°C 25°C 85°C ICC (mA) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 142. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1.2 85°C 25°C -40°C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Figure 143. Idle Supply Current vs. VCC (32 kHz External Oscillator) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 0.04 25°C 0.035 0.03 ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Down Supply Current Figure 144. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 2.5 85°C 2 1.5 ICC (uA) -40°C 25°C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 145. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 0.025 0.02 85°C 25°C -40°C ICC (mA) 0.015 0.01 0.005 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Save Supply Current Figure 146. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 16 14 25°C 12 ICC (uA) 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Standby Supply Current Figure 147. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 90 80 70 ICC (uA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 148. Standby Supply Current vs. V CC (1 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 1 MHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
Figure 149. Standby Supply Current vs. V CC (2 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 2 MHz RESONATOR, WATCHDOG TIMER DISABLED 100 90 80 ICC (uA) 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 150. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 2 MHz XTAL, WATCHDOG TIMER DISABLED 100 90 80 ICC (uA) 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Figure 151. Standby Supply Current vs. V CC (4 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 152. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
Figure 153. Standby Supply Current vs. V CC (6 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 180 160 140 ICC (uA) 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 154. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 6 MHz XTAL, WATCHDOG TIMER DISABLED 180 160 140 ICC (uA) 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Pin Pullup Figure 155. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 140 25°C 85°C 120 -40°C IOP (uA) 100 80 60 40 20 0 0 1 2 3 VOP (V) Figure 156. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 80 85°C 70 25°C 60 -40°C IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
Figure 157. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 120 -40°C 25°C 100 85°C IRESET (uA) 80 60 40 20 0 0 1 2 3 VRESET (V) Figure 158. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 -40°C 25°C 50 85°C IRESET (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega8535(L) Pin Driver Strength Figure 159. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 -40°C 70 25°C IOH (mA) 60 85°C 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VOH (V) Figure 160. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40°C 25 25°C 85°C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
Figure 161. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 IOL (mA) 80 -40°C 70 25°C 60 85°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 162. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 -40°C 30 25 °C 25 IOL (mA) 85 °C 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega8535(L) Pin Thresholds And Hysteresis Figure 163. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 -40°C 85°C 25°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 164. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2 -40°C 25°C 85°C Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 165. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.7 85°C 25°C -40°C 0.6 Threshold (V) 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 166. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 2 Threshold (V) -40°C 1.5 25°C 85°C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Figure 167. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85°C -40°C 2.5 Threshold (V) 25°C 2 1.5 1 0.5 2.5 3 3.5 4 4.5 5 5.5 5 5.5 VCC (V) Figure 168. Reset Input Pin Hysteresis vs. VCC RESET INPUT PIN HYSTERESIS vs. VCC 0.6 -40°C 0.5 Threshold (V) 0.4 25°C 0.3 0.2 85°C 0.1 0 2.5 3 3.5 4 4.
BOD Thresholds And Analog Comparator Offset Figure 169. BOD Thresholds vs. Temperature (BOD Level is 4.0V) BOD THRESHOLDS vs. TEMPERATURE BOD LEVEL IS 4.0 V 4 Rising VCC 3.95 Threshold (V) 3.9 3.85 3.8 Falling VCC 3.75 3.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (C) Figure 170. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BOD LEVEL IS 2.7 V 2.85 2.8 Rising VCC Threshold (V) 2.75 2.7 2.65 Falling VCC 2.6 2.
ATmega8535(L) Figure 171. Bandgap Voltage vs. VCC BANDGAP vs. VCC 1.226 -40°C 1.224 25°C 85°C Bandgap Voltage (V) 1.222 1.22 1.218 1.216 1.214 1.212 1.21 1.208 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 172. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 0.002 Comparator Offset Voltage (V) 0.001 0 -0.001 -0.002 25°C -0.003 85°C -0.004 -0.005 -40°C -0.006 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 173. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 0.002 Comparator Offset Voltage (V) 0.001 0 -0.001 25°C -0.002 85°C -0.003 -40°C -0.004 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Internal Oscillator Speed Figure 174. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1300 -40°C 25 °C 85°C 1250 FRC (kHz) 1200 1150 1100 1050 1000 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Figure 175. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 9 8.5 FRC (MHz) 8 5.5V 7.5 4.0V 7 2.7V 6.5 6 -50 -30 -10 10 30 50 70 90 110 Temp (C˚) Figure 176. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 8.5 -40°C 8.3 25°C 8.1 FRC (MHz) 7.9 85°C 7.7 7.5 7.3 7.1 6.9 6.7 6.5 2.5 3 3.5 4 4.5 5 5.
Figure 177. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs.OSCCAL VALUE 18 16 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 178. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.2 4.1 4 FRC (MHz) 5.5V 3.9 3.8 4.0V 3.7 2.7V 3.6 3.
ATmega8535(L) Figure 179. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. VCC 4.2 -40°C 4.1 25°C 4 85°C FRC (MHz) 3.9 3.8 3.7 3.6 3.5 3.4 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 180. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs.
Figure 181. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.1 2.05 2 FRC (MHz) 5.5V 1.95 1.9 4.0V 1.85 2.7V 1.8 1.75 -50 -30 -10 10 30 50 70 90 110 Temp (C˚) Figure 182. Calibrated 2 MHz RC Oscillator Frequency vs. VCC CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. VCC 2.15 2.1 -40°C 2.05 25°C FRC (MHz) 2 85°C 1.95 1.9 1.85 1.8 1.75 1.7 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Figure 183. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 4 3.5 3 FRC (MHz) 2.5 2 1.5 1 0.5 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 184. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.04 1.02 1 FRC (MHz) 5.5V 0.98 0.96 4.0V 0.94 0.92 2.7V 0.
Figure 185. Calibrated 1 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. VCC FRC (MHz) 1.05 1.03 -40°C 1.01 25°C 0.99 85°C 0.97 0.95 0.93 0.91 0.89 0.87 0.85 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 186. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 2 1.8 1.6 FRC (MHz) 1.4 1.2 1 0.8 0.6 0.4 0.
ATmega8535(L) Current Consumption Of Peripheral Units Figure 187. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 0.025 -40°C 0.02 25°C 85°C ICC (mA) 0.015 0.01 0.005 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 188. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AVCC 600 500 -40°C 25°C ICC (uA) 400 85°C 300 200 100 0 2.5 3 3.5 4 4.5 5 5.
Figure 189. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 250 25°C 85°C -40°C 200 ICC (uA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 190. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 120 100 85°C 25°C ICC (uA) 80 -40°C 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) Figure 191. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 12 10 -40°C ICC (mA) 8 25°C 85°C 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Current Consumption In Reset And Reset Pulsewidth Figure 192. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 3 5.5V 2.5 5.0V ICC (mA) 2 4.5V 4.0V 1.5 3.3V 3.0V 2.7V 1 0.5 0 0 0.1 0.2 0.3 0.4 0.
Figure 193. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 25 5.5V 5.0V 20 4.5V ICC (mA) 15 4.0V 10 3.3V 5 3.0V 2.7V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 194. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC 1200 1000 Pulsewidth (ns) 800 600 85°C 25°C 400 -40°C 200 0 2.5 3 3.5 4 4.5 5 5.
ATmega8535(L) .
Register Summary (Continued) Address Name 0x00 (0x20) TWBR Notes: 300 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Two-wire Serial Interface Bit Rate Register Bit 2 Bit 1 Bit 0 Page 181 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the status flags are cleared by writing a logical one to them.
ATmega8535(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two
Mnemonics Operands Description Operation Flags MOV Rd, Rr Move Between Registers None 1 MOVW Rd, Rr Copy Register Word Rd ← Rr Rd+1:Rd ← Rr+1:Rr #Clocks None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc.
ATmega8535(L) Mnemonics Description Operation Flags SLEEP Operands Sleep (see specific descr. for Sleep function) None #Clocks 1 WDR BREAK Watchdog Reset Break (see specific descr.
Ordering Information Speed (MHz) 8 16 Note: Power Supply 2.7 - 5.5V 4.5 - 5.
ATmega8535(L) Package Type 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44M1-A 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.
Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.
ATmega8535(L) 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C eB Notes: COMMON DIMENSIONS (Unit of Measure = mm) REF 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.
44J 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
ATmega8535(L) 44M1-A D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW 0.25 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig.
Errata The revision letter refer to the device revision. ATmega8535 Rev. A and B • First Analog Comparator conversion may be delayed • Asynchronous Oscillator does not stop in Power-down 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices.
ATmega8535(L) Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 2502J- 08/06 to Rev. 2502K- 10/06 1. Updated TOP/BOTTOM description for all Timer/Counters Fast PWM mode. Changes from Rev. 2502I- 06/06 to Rev. 2502J- 08/06 1. Updated “Ordering Information” on page 304. Changes from Rev. 2502H- 04/06 to Rev. 2502I- 06/06 1.
Changes from Rev. 2502C-04/03 to Rev. 2502D-09/03 1. Removed “Advance Information” and some TBD’s from the datasheet. 2. Added note to “Pinout ATmega8535” on page 2. 3. Updated “Reset Characteristics” on page 37. 4. Updated “Absolute Maximum Ratings” and “DC Characteristics” in “Electrical Characteristics” on page 255. 5. Updated Table 111 on page 258. 6. Updated “ADC Characteristics” on page 263. 7. Updated “ATmega8535 Typical Characteristics” on page 266. 8.
ATmega8535(L) 14. Updated “ADC Characteristics” on page 263. 14. Updated “Register Summary” on page 299. 15. Various Timer 1 corrections. 16. Added WD_FUSE period in Table 108 on page 253. Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02 1. Canged the Endurance on the Flash to 10,000 Write/Erase Cycles.
ATmega8535(L) 2502K–AVR–10/06
ATmega8535(L) Table of Contents Features................................................................................................ 1 Pin Configurations............................................................................... 2 Disclaimer ............................................................................................................. 2 Overview............................................................................................... 3 Block Diagram ............................
Standby Mode..................................................................................................... 34 Extended Standby Mode .................................................................................... 34 Minimizing Power Consumption ......................................................................... 35 System Control and Reset ................................................................ 36 Internal Voltage Reference ..........................................................
ATmega8535(L) Overview........................................................................................................... Timer/Counter Clock Sources........................................................................... Counter Unit...................................................................................................... Output Compare Unit........................................................................................ Compare Match Output Unit ..............................
Prescaling and Conversion Timing ................................................................... Changing Channel or Reference Selection ...................................................... ADC Noise Canceler......................................................................................... ADC Conversion Result.................................................................................... 209 212 214 218 Boot Loader Support – Read-While-Write Self-Programming .....
ATmega8535(L) Errata ................................................................................................ 310 ATmega8535 Rev. A and B..................................................................................................... 310 Datasheet Revision History ............................................................ 311 Changes from Rev. 2502J- 08/06 to Rev. 2502K- 10/06.................................. Changes from Rev. 2502I- 06/06 to Rev. 2502J- 08/06 ..............................
vi ATmega8535(L) 2502K–AVR–10/06
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