Datasheet

51
ATmega8515(L)
2512G–AVR–03/05
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the
Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-
rithm described above. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 52.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 21.
The following code example shows one assembly and one C function for turning off the
WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts
globally) so that no interrupts will occur during execution of these functions.
Table 21. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0
Number of WDT
Oscillator Cycles
Typical Time-out
at V
CC
= 3.0V
Typical Time-out
at V
CC
= 5.0V
0 0 0 16K (16,384) 17.1 ms 16.3 ms
0 0 1 32K (32,768) 34.3 ms 32.5 ms
0 1 0 64K (65,536) 68.5 ms 65 ms
0 1 1 128K (131,072) 0.14 s 0.13 s
1 0 0 256K (262,144) 0.27 s 0.26 s
1 0 1 512K (524,288) 0.55 s 0.52 s
1 1 0 1,024K (1,048,576) 1.1 s 1.0 s
1 1 1 2,048K (2,097,152) 2.2 s 2.1 s
Assembly Code Example
WDT_off:
; Write logical one to WDCE and WDE
ldi r16, (1<<WDCE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCR, r16
ret
C Code Example
void WDT_off(void)
{
/* Write logical one to WDCE and WDE */
WDTCR = (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}