Datasheet

ATmega8515(L)

2512G–AVR–03/05

Figure 9. Data Memory Map

Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clk

CPU

cycles as described in Figure

10.

Figure 10. On-chip Data SRAM Access Cycles

32 Registers

64 I/O Registers

Internal SRAM

(512 x 8)

$0000 - $001F

$0020 - $005F

$0260

$025F

$FFFF

$0060

Data Memory

External SRAM

(0 - 64K x 8)

clk

Data

ddress

Address Valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction