Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 32 (7x7) 8-Bit 16 MHz I/O number 23

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Table Of Contents

Features
Pin Configurations
Overview
- Block Diagram
- Disclaimer
- Pin Descriptions
Resources
Data Retention
About Code Examples
Atmel AVR CPU Core
- Introduction
- Architectural Overview
- Arithmetic Logic Unit – ALU
- Status Register
- General Purpose Register File
  - The X-register, Y- register and Z-register
- Stack Pointer
- Instruction Execution Timing
- Reset and Interrupt Handling
  - Interrupt Response Time
AVR ATmega8 Memories
- In-System Reprogrammable Flash Program Memory
- SRAM Data Memory
- Data Memory Access Times
- EEPROM Data Memory
- I/O Memory
System Clock and Clock Options
- Clock Systems and their Distribution
- Clock Sources
- Crystal Oscillator
- Low-frequency Crystal Oscillator
- External RC Oscillator
- Calibrated Internal RC Oscillator
  - Oscillator Calibration Register – OSCCAL
- External Clock
- Timer/Counter Oscillator
Power Management and Sleep Modes
- MCU Control Register – MCUCR
- Idle Mode
- ADC Noise Reduction Mode
- Power-down Mode
- Power-save Mode
- Standby Mode
- Minimizing Power Consumption
System Control and Reset
- Resetting the AVR
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Control and Status Register – MCUCSR
- Internal Voltage Reference
  - Voltage Reference Enable Signals and Start-up Time
- Watchdog Timer
  - Watchdog Timer Control Register – WDTCR
- Timed Sequences for Changing the Configuration of the Watchdog Timer
  - Safety Level 1 (WDTON Fuse Unprogrammed)
  - Safety Level 2 (WDTON Fuse Programmed)
Interrupts
- Interrupt Vectors in ATmega8
  - Moving Interrupts Between Application and Boot Space
  - General Interrupt Control Register – GICR
I/O Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O Ports
External Interrupts
- MCU Control Register – MCUCR
- General Interrupt Control Register – GICR
- General Interrupt Flag Register – GIFR
8-bit Timer/Counter0
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
Timer/Counter0 and Timer/Counter1 Prescalers
- Internal Clock Source
- Prescaler Reset
- External Clock Source
- Special Function IO Register – SFIOR
16-bit Timer/Counter1
- Overview
- Accessing 16-bit Registers
  - Reusing the Temporary High Byte Register
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
8-bit Timer/Counter2 with PWM and Asynchronous Operation
- Overview
  - Registers
  - Definitions
- Timer/Counter Clock Sources
- Counter Unit
- Output Compare Unit
- Compare Match Output Unit
  - Compare Output Mode and Waveform Generation
- Modes of Operation
- Timer/Counter Timing Diagrams
- 8-bit Timer/Counter Register Description
- Asynchronous Operation of the Timer/Counter
- Timer/Counter Prescaler
  - Special Function IO Register – SFIOR
Serial Peripheral Interface – SPI
- SS Pin Functionality
- Data Modes
USART
- Overview
  - AVR USART vs. AVR UART – Compatibility
- Clock Generation
- Frame Formats
  - Parity Bit Calculation
- USART Initialization
- Data Transmission – The USART Transmitter
- Data Reception – The USART Receiver
- Asynchronous Data Reception
- Multi-processor Communication Mode
  - Using MPCM
- Accessing UBRRH/UCSRC Registers
  - Write Access
  - Read Access
- USART Register Description
- Examples of Baud Rate Setting
Two-wire Serial Interface
- Features
- Two-wire Serial Interface Bus Definition
  - TWI Terminology
  - Electrical Interconnection
- Data Transfer and Frame Format
- Multi-master Bus Systems, Arbitration and Synchronization
- Overview of the TWI Module
- TWI Register Description
- Using the TWI
- Transmission Modes
- Multi-master Systems and Arbitration
Analog Comparator
- Special Function IO Register – SFIOR
- Analog Comparator Control and Status Register – ACSR
- Analog Comparator Multiplexed Input
Analog-to- Digital Converter
- Features
- Starting a Conversion
- Prescaling and Conversion Timing
- Changing Channel or Reference Selection
  - ADC Input Channels
  - ADC Voltage Reference
- ADC Noise Canceler
- ADC Conversion Result
Boot Loader Support – Read- While-Write Self- Programming
- Boot Loader Features
- Application and Boot Loader Flash Sections
  - Application Section
  - BLS – Boot Loader Section
- Read-While-Write and No Read- While-Write Flash Sections
  - RWW – Read-While- Write Section
  - NRWW – No Read- While-Write Section
- Boot Loader Lock Bits
- Entering the Boot Loader Program
  - Store Program Memory Control Register – SPMCR
- Addressing the Flash During Self- Programming
- Self-Programming the Flash
Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
  - Latching of Fuses
- Signature Bytes
- Calibration Byte
- Page Size
- Parallel Programming Parameters, Pin Mapping, and Commands
  - Signal Names
- Parallel Programming
- Serial Downloading
- Serial Programming Pin Mapping
Electrical Characteristics – TA = -40°C to 85°C
- Absolute Maximum Ratings*
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- Two-wire Serial Interface Characteristics
- SPI Timing Characteristics
- ADC Characteristics
Electrical Characteristics – TA = -40°C to 105°C
- Absolute Maximum Ratings*
- DC Characteristics TA = -40°C to 105°C, VCC = 2.7V to 5.5V (unless otherwise noted)
ATmega8 Typical Characteristics – TA = -40°C to 85°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
ATmega8 Typical Characteristics – TA = -40°C to 105°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
Register Summary
Instruction Set Summary
Ordering Information
Packaging Information
- 32A
- 28P3
- 32M1-A
Errata
- ATmega8 Rev. D to I, M
Datasheet Revision History
- Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013
- Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
Table of Contents

311

2486AA–AVR–02/2013

ATmega8(L)

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd  Rd + Rr Z, C, N, V, H 1

ADC Rd, Rr Add with Carry two Registers Rd  Rd + Rr + C Z, C, N, V, H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl  Rdh:Rdl + K Z, C, N, V, S 2

SUB Rd, Rr Subtract two Registers Rd  Rd - Rr Z, C, N, V, H 1

SUBI Rd, K Subtract Constant from Register Rd  Rd - K Z, C, N, V, H 1

SBC Rd, Rr Subtract with Carry two Registers Rd  Rd - Rr - C Z, C, N, V, H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd  Rd - K - C Z, C, N ,V, H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl  Rdh:Rdl - K Z, C, N, V, S 2

AND Rd, Rr Logical AND Registers Rd Rd  Rr Z, N, V 1

ANDI Rd, K Logical AND Register and Constant Rd  Rd K Z, N, V 1

OR Rd, Rr Logical OR Registers Rd  Rd v Rr Z, N, V 1

ORI Rd, K Logical OR Register and Constant Rd Rd v K Z, N, V 1

EOR Rd, Rr Exclusive OR Registers Rd  Rd  Rr Z, N, V 1

COM Rd One’s Complement Rd  0xFF  Rd Z, C, N, V 1

NEG Rd Two’s Complement Rd  0x00  Rd Z, C, N, V, H 1

SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z, N, V 1

CBR Rd,K Clear Bit(s) in Register Rd  Rd  (0xFF - K) Z, N, V 1

INC Rd Increment Rd  Rd + 1 Z, N, V 1

DEC Rd Decrement Rd  Rd  1 Z, N, V 1

TST Rd Test for Zero or Minus Rd  Rd  Rd Z, N, V 1

CLR Rd Clear Register Rd  Rd  Rd Z, N, V 1

SER Rd Set Register Rd  0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0  Rd x Rr Z, C 2

MULS Rd, Rr Multiply Signed R1:R0  Rd x Rr Z, C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0  Rd x Rr Z, C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0  (Rd x Rr) << 1 Z, C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0  (Rd x Rr) << 1 Z, C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0  (Rd x Rr) << 1 Z, C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC  Z None 2

RCALL k Relative Subroutine Call PC  PC + k + 1 None 3

ICALL Indirect Call to (Z) PC  ZNone3

RET Subroutine Return PC  STACK None 4

RETI Interrupt Return PC  STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd  Rr Z, N, V, C, H 1

CPC Rd,Rr Compare with Carry Rd  Rr  C Z, N, V, C, H 1

CPI Rd,K Compare Register with Immediate Rd  K Z, N, V, C, H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC  PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC  PC + 2 or 3 None 1 / 2 / 3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC  PC + 2 or 3 None 1 / 2 / 3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC  PC + 2 or 3 None 1 / 2 / 3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1 / 2

BRLT k Branch if Less Than Zero, Signed if (N  V= 1) then PC  PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1 / 2