Datasheet
Table Of Contents
- Features
- Pin Configurations
- Overview
- Resources
- Data Retention
- About Code Examples
- Atmel AVR CPU Core
- AVR ATmega8 Memories
- System Clock and Clock Options
- Power Management and Sleep Modes
- System Control and Reset
- Interrupts
- I/O Ports
- Introduction
- Ports as General Digital I/O
- Alternate Port Functions
- Register Description for I/O Ports
- The Port B Data Register – PORTB
- The Port B Data Direction Register – DDRB
- The Port B Input Pins Address – PINB
- The Port C Data Register – PORTC
- The Port C Data Direction Register – DDRC
- The Port C Input Pins Address – PINC
- The Port D Data Register – PORTD
- The Port D Data Direction Register – DDRD
- The Port D Input Pins Address – PIND
- External Interrupts
- 8-bit Timer/Counter0
- Timer/Counter0 and Timer/Counter1 Prescalers
- 16-bit Timer/Counter1
- Overview
- Accessing 16-bit Registers
- Timer/Counter Clock Sources
- Counter Unit
- Input Capture Unit
- Output Compare Units
- Compare Match Output Unit
- Modes of Operation
- Timer/Counter Timing Diagrams
- 16-bit Timer/Counter Register Description
- Timer/Counter 1 Control Register A – TCCR1A
- Timer/Counter 1 Control Register B – TCCR1B
- Timer/Counter 1 – TCNT1H and TCNT1L
- Output Compare Register 1 A – OCR1AH and OCR1AL
- Output Compare Register 1 B – OCR1BH and OCR1BL
- Input Capture Register 1 – ICR1H and ICR1L
- Timer/Counter Interrupt Mask Register – TIMSK(1)
- Timer/Counter Interrupt Flag Register – TIFR(1)
- 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- Serial Peripheral Interface – SPI
- USART
- Two-wire Serial Interface
- Analog Comparator
- Analog-to- Digital Converter
- Boot Loader Support – Read- While-Write Self- Programming
- Boot Loader Features
- Application and Boot Loader Flash Sections
- Read-While-Write and No Read- While-Write Flash Sections
- Boot Loader Lock Bits
- Entering the Boot Loader Program
- Addressing the Flash During Self- Programming
- Self-Programming the Flash
- Performing Page Erase by SPM
- Filling the Temporary Buffer (Page Loading)
- Performing a Page Write
- Using the SPM Interrupt
- Consideration While Updating BLS
- Prevent Reading the RWW Section During Self-Programming
- Setting the Boot Loader Lock Bits by SPM
- EEPROM Write Prevents Writing to SPMCR
- Reading the Fuse and Lock Bits from Software
- Preventing Flash Corruption
- Programming Time for Flash when using SPM
- Simple Assembly Code Example for a Boot Loader
- ATmega8 Boot Loader Parameters
- Memory Programming
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Page Size
- Parallel Programming Parameters, Pin Mapping, and Commands
- Parallel Programming
- Enter Programming Mode
- Considerations for Efficient Programming
- Chip Erase
- Programming the Flash
- Programming the EEPROM
- Reading the Flash
- Reading the EEPROM
- Programming the Fuse Low Bits
- Programming the Fuse High Bits
- Programming the Lock Bits
- Reading the Fuse and Lock Bits
- Reading the Signature Bytes
- Reading the Calibration Byte
- Parallel Programming Characteristics
- Serial Downloading
- Serial Programming Pin Mapping
- Electrical Characteristics – TA = -40°C to 85°C
- Electrical Characteristics – TA = -40°C to 105°C
- ATmega8 Typical Characteristics – TA = -40°C to 85°C
- Active Supply Current
- Idle Supply Current
- Power-down Supply Current
- Power-save Supply Current
- Standby Supply Current
- Pin Pull-up
- Pin Driver Strength
- Pin Thresholds and Hysteresis
- Bod Thresholds and Analog Comparator Offset
- Internal Oscillator Speed
- Current Consumption of Peripheral Units
- Current Consumption in Reset and Reset Pulsewidth
- ATmega8 Typical Characteristics – TA = -40°C to 105°C
- Register Summary
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Errata
- Datasheet Revision History
- Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013
- Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- Table of Contents
11
2486AA–AVR–02/2013
ATmega8(L)
Arithmetic Logic
Unit – ALU
The high-performance Atmel
®
AVR
®
ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories – arithmetic, logical, and bit-functions. Some implementa-
tions of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. For a detailed description, see “Instruction Set Summary” on
page 311.
Status Register The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the Instruction Set Reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
Bit 76543210
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0