Features • High-performance, Low-power Atmel®AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 8Kbytes of In-System Self-programmable Flash program memory – 512Bytes EEPROM – 1Kbyte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
ATmega8(L) Pin Configurations PDIP (RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A) 32 31 30 29 28 27 26 25 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SD
ATmega8(L) Overview The Atmel®AVR® ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1.
ATmega8(L) The Atmel®AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega8(L) Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/ TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
ATmega8(L) AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC. AREF AREF is the analog reference pin for the A/D Converter. ADC7..6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter.
ATmega8(L) Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
ATmega8(L) About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
ATmega8(L) Atmel AVR CPU Core Introduction This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 2.
ATmega8(L) can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-register, Y-register, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
ATmega8(L) Arithmetic Logic Unit – ALU The high-performance Atmel®AVR® ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions.
ATmega8(L) • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega8(L) The X-register, Yregister and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in Figure 4. Figure 4.
ATmega8(L) Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5.
ATmega8(L) When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag.
ATmega8(L) When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example.
ATmega8(L) AVR ATmega8 Memories This section describes the different memories in the Atmel®AVR® ATmega8. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega8 contains 8Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega8(L) SRAM Data Memory Figure 8 shows how the Atmel®AVR® SRAM Memory is organized. The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
ATmega8(L) Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 9. Figure 9. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address Valid Write Data WR Read Data RD Memory Vccess Instruction EEPROM Data Memory Next Instruction The ATmega8 contains 512bytes of data EEPROM memory.
ATmega8(L) The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero. • Bits 8..0 – EEAR8..
ATmega8(L) erwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero 2. Wait until SPMEN in SPMCR becomes zero 3. Write new EEPROM address to EEAR (optional) 4. Write new EEPROM data to EEDR (optional) 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR 6.
ATmega8(L) The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega8(L) The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega8(L) tion circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. I/O Memory The I/O space definition of the ATmega8 is shown in “Register Summary” on page 309. All Atmel®AVR® ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space.
ATmega8(L) System Clock and Clock Options Clock Systems and their Distribution Figure 10 presents the principal clock systems in the Atmel®AVR® and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 33. The clock systems are detailed Figure 10. Figure 10.
ATmega8(L) Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. The Asynchronous Timer/Counter uses the same XTAL pins as the CPU main clock but requires a CPU main clock frequency of more than four times the Oscillator frequency.
ATmega8(L) Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 11. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a full rail-torail swing on the output.
ATmega8(L) Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 4.1ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.
ATmega8(L) least 22pF. By programming the CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 12. External RC Configuration VCC R NC XTAL2 XTAL1 C GND The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 7. Table 7. External RC Oscillator Operating Modes CKSEL3..0 Frequency Range (MHz) 0101 0.
ATmega8(L) Calibrated Internal The calibrated internal RC Oscillator provides a fixed 1.0MHz, 2.0MHz, 4.0MHz, or 8.0MHz clock. All frequencies are nominal values at 5V and 25C. This clock may be selected as the RC Oscillator system clock by programming the CKSEL Fuses as shown in Table 9. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option.
ATmega8(L) Oscillator Calibration Register – OSCCAL Bit Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency.
ATmega8(L) External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, and XTAL2 and GND. Figure 13. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12.
ATmega8(L) Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
ATmega8(L) Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
ATmega8(L) Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in 6 clock cycles. Table 14.
ATmega8(L) Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 40 for details on how to configure the Brown-out Detector.
ATmega8(L) System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa.
ATmega8(L) Figure 14. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Control and Status Register (MCUCSR) Brown-Out Reset Circuit BODEN BODLEVEL Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 15. Reset Characteristics Symbol Parameter Condition Min Power-on Reset Threshold Voltage (rising)(1) VPOT Typ Max 1.4 2.3 V Power-on Reset Threshold Voltage (falling) 1.3 2.
ATmega8(L) Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 15 on page 38. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATmega8(L) External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15 on page 38) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay counter starts the MCU after the time-out period tTOUT has expired. Figure 17.
ATmega8(L) Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. Refer to page 43 for details on operation of the Watchdog Timer. Figure 19. Watchdog Reset During Operation CC CK MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
ATmega8(L) Internal Voltage Reference ATmega8 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 16.
ATmega8(L) Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 17 on page 44. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
ATmega8(L) • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts 2.
ATmega8(L) Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels. Separate procedures are described for each level.
ATmega8(L) Interrupts Interrupt Vectors in ATmega8 This section describes the specifics of the interrupt handling performed by the ATmega8. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 14. Table 18. Reset and Interrupt Vectors Vector No.
ATmega8(L) Table 19. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL 1 Reset Address Interrupt Vectors Start Address 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x001 Note: 1. The Boot Reset Address is shown in Table 82 on page 213.
ATmega8(L) When the BOOTRST Fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code $000 ; $001 rjmp RESET:ldi Comments RESET ; Reset handler r16,high(RAMEND); Main program start $002 out SPH,r16 ; Set Stack Pointer to top of RAM $003 ldi r16,low(RAMEND) $004 out SPL,r16 $005 sei $006 ; En
ATmega8(L) When the BOOTRST Fuse is programmed, the boot section size set to 2Kbytes, and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments ; Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR .org $c00 $c00 $c01 rjmp rjmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler ...
ATmega8(L) • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
ATmega8(L) I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega8(L) Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 on page 52 shows a functional description of one I/O port pin, here generically called Pxn. Figure 22.
ATmega8(L) When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports.
ATmega8(L) goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1-½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock.
ATmega8(L) The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega8(L) Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega8(L) Table 21 summarizes the function of the overriding signals. The pin and port indexes from Figure 25 on page 56 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 21. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega8(L) Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 ACME PUD PSR2 PSR10 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 52 for more details about this feature.
ATmega8(L) • SCK – Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. • MISO – Port B, Bit 4 MISO: Master Data input, Slave Data output pin for SPI channel.
ATmega8(L) Table 23. Overriding Signals for Alternate Functions in PB7..
ATmega8(L) Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 25. Table 25.
ATmega8(L) • ADC1 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. • ADC0 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. Table 26 and Table 27 relate the alternate functions of Port C to the overriding signals shown in Figure 25 on page 56. Table 26. Overriding Signals for Alternate Functions in PC6..
ATmega8(L) Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 28. Table 28.
ATmega8(L) Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/AIN1 PD6/AIN0 PD5/T1 PD4/XCK/T0 PUOE 0 0 0 0 PUO 0 0 0 0 OOE 0 0 0 0 OO 0 0 0 0 PVOE 0 0 0 UMSEL PVO 0 0 0 XCK OUTPUT DIEOE 0 0 0 0 DIEO 0 0 0 0 DI – – T1 INPUT XCK INPUT / T0 INPUT AIO AIN1 INPUT AIN0 INPUT – – Table 30. Overriding Signals for Alternate Functions in PD3..
ATmega8(L) Register Description for I/O Ports The Port B Data Register – PORTB The Port B Data Direction Register – DDRB The Port B Input Pins Address – PINB The Port C Data Register – PORTC The Port C Data Direction Register – DDRC The Port C Input Pins Address – PINC The Port D Data Register – PORTD The Port D Data Direction Register – DDRD The Port D Input Pins Address – PIND Bit 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R/W R/W R/W R
ATmega8(L) External Interrupts The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register – MCUCR.
ATmega8(L) • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 32. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
ATmega8(L) • Bit 6 – INTF0: External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the Ibit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.
ATmega8(L) 8-bit Timer/Counter0 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Frequency Generator • External Event Counter • 10-bit Clock Prescaler Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
ATmega8(L) Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 73. Counter Unit The main part of the 8-bit Timer/Counter is the programmable counter unit.
ATmega8(L) Figure 28. Timer/Counter Timing Diagram, No Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 29 shows the same timing data, but with the prescaler enabled. Figure 29.
ATmega8(L) Table 34. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge 1 1 1 External clock source on T0 pin.
ATmega8(L) Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
ATmega8(L) sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 31.
ATmega8(L) 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement.
ATmega8(L) Figure 32. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int. Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int. Req.) Waveform Generation = OCnA DATA BUS OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
ATmega8(L) The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see “Analog Comparator” on page 186). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
ATmega8(L) of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle as the Low byte is read. Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16bit registers does not involve using the temporary register. To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be read before the High byte.
ATmega8(L) Assembly Code Example(1) TIM16_ReadTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore Global Interrupt Flag */ SREG = sreg; return i; } Note: 1.
ATmega8(L) The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega8(L) Figure 33. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int. Req.
ATmega8(L) The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 34. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 34.
ATmega8(L) unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 30 on page 73). The edge detector is also identical.
ATmega8(L) Figure 35 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 35. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf.
ATmega8(L) Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real Compare Match had occurred (the COM1x1:0 bits settings define whether the OC1x pin is set, cleared or toggled).
ATmega8(L) Figure 36. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATABUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega8(L) Compare Output Mode and Waveform Generation The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 36 on page 96. For fast PWM mode refer to Table 37 on page 96, and for phase correct and phase and frequency correct PWM refer to Table 38 on page 97.
ATmega8(L) Figure 37. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega8(L) maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log TOP + 1 R FPWM = ----------------------------------log 2 In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle.
ATmega8(L) Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
ATmega8(L) tion. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 39.
ATmega8(L) the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega8(L) Figure 40. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
ATmega8(L) output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures.
ATmega8(L) ing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 43.
ATmega8(L) 16-bit Timer/Counter Register Description Timer/Counter 1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for channel B The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B respectively) behavior.
ATmega8(L) Table 38 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 38. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
ATmega8(L) Table 39.
ATmega8(L) Table 40. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source. (Timer/Counter stopped) 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge 1 1 1 External clock source on T1 pin.
ATmega8(L) The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare Interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte Register (TEMP).
ATmega8(L) Timer/Counter Interrupt Flag Register – TIFR(1) Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIFR 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section.
ATmega8(L) 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
ATmega8(L) Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
ATmega8(L) Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 46 shows a block diagram of the counter and its surrounding environment. Figure 46. Counter Unit Block Diagram TOVn (Int. Req.
ATmega8(L) Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed.
ATmega8(L) Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).
ATmega8(L) Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 48 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega8(L) Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the nonPWM modes refer to Table 43 on page 115. For fast PWM mode, refer to Table 44 on page 115, and for phase correct PWM refer to Table 45 on page 116.
ATmega8(L) Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events.
ATmega8(L) Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM.
ATmega8(L) The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.
ATmega8(L) The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 45 on page 116).
ATmega8(L) Figure 53 shows the same timing data, but with the prescaler enabled. Figure 53. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 54 shows the setting of OCF2 in all modes except CTC mode. Figure 54.
ATmega8(L) Figure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 55.
ATmega8(L) Table 42. Waveform Generation Mode Bit Description Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation(1) TOP Update of OCR2 TOV2 Flag Set 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
ATmega8(L) Table 45 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 45. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting Note: Description 1.
ATmega8(L) Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – – AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin.
ATmega8(L) write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that, for example, writing to TCNT2 does not disturb an OCR2 write in progress.
ATmega8(L) • Timer/Counter Interrupt Mask Register – TIMSK During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag.
ATmega8(L) Figure 56. Prescaler for Timer/Counter2 clkT2S PSR2 clkT2S/1024 clkT2S/256 clkT2S/8 AS2 clkT2S/128 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/64 clkI/O clkT2S/32 Timer/Counter Prescaler 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
ATmega8(L) Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices.
ATmega8(L) byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line.
ATmega8(L) The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega8(L) The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega8(L) SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega8(L) • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
ATmega8(L) • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt Handling Vector.
ATmega8(L) Figure 59. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 60.
ATmega8(L) USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly-flexible serial communication device.
ATmega8(L) The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (transfer clock) pin is only used by synchronous transfer mode.
ATmega8(L) Figure 62. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector DDR_XCK 0 UMSEL 1 xcko UCPOL txclk 1 1 0 rxclk Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal).
ATmega8(L) Table 52.
ATmega8(L) Figure 63. Synchronous Mode XCK Timing UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 63 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.
ATmega8(L) The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits.
ATmega8(L) Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<
ATmega8(L) Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid– The USART den by the USART and given the function as the Transmitter’s serial output. The baud rate, Transmitter mode of operation and frame format must be set up once before doing any transmissions.
ATmega8(L) Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega8(L) UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
ATmega8(L) bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRA & (1<
ATmega8(L) The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits.
ATmega8(L) Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero.
ATmega8(L) Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled.
ATmega8(L) the figure. The clock recovery logic then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition.
ATmega8(L) Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see Table 53) base frequency, the Receiver will not be able to synchronize the frames to the start bit.
ATmega8(L) The recommendations of the maximum Receiver baud rate error was made under the assumption that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the Receivers Baud Rate error. The Receiver’s system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range.
ATmega8(L) Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. Accessing UBRRH/UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location.
ATmega8(L) Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents.
ATmega8(L) USART Register Description USART I/O Data Register – UDR Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDR (Read) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location.
ATmega8(L) • Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received (that is, when the first stop bit of the next character in the receive buffer is zero). This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA. • Bit 3 – DOR: Data OverRun This bit is set if a Data OverRun condition is detected.
ATmega8(L) • Bit 3 – TXEN: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed (that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted). When disabled, the Transmitter will no longer override the TxD port.
ATmega8(L) • Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set. Table 56.
ATmega8(L) • Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 59.
ATmega8(L) Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 60. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega8(L) Table 61. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.
ATmega8(L) Table 62. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.
ATmega8(L) Table 63. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.
ATmega8(L) Two-wire Serial Interface Features • • • • • • • • • • Two-wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
ATmega8(L) Electrical Interconnection As depicted in Figure 68 on page 157, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
ATmega8(L) Figure 70. START, REPEATED START and STOP conditions SDA SCL START Address Packet Format STOP REPEATED START START STOP All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
ATmega8(L) Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
ATmega8(L) Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
ATmega8(L) Figure 75. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
ATmega8(L) Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 76. All registers drawn in a thick line are accessible through the AVR data bus. Figure 76.
ATmega8(L) Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.
ATmega8(L) The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition • After the TWI has transmitted SLA+R/W • After the TWI has transmitted an address byte • After the TWI has lost arbitration • After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave • When a bus error has occurred due to an illega
ATmega8(L) • Bit 6 – TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received 2. A general call has been received, while the TWGCE bit in the TWAR is set 3.
ATmega8(L) • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 1..0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 65. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator Unit” on page 164. The value of TWPS1..0 is used in the equation.
ATmega8(L) • Bits 7..1 – TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit. • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition.
ATmega8(L) 3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data.
ATmega8(L) Assembly Code Example 1 ldi r16, (1<
ATmega8(L) Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
ATmega8(L) Figure 78. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag.
ATmega8(L) enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 66.
ATmega8(L) Figure 79.
ATmega8(L) Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (see Figure 80). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
ATmega8(L) After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 67.
ATmega8(L) Figure 81.
ATmega8(L) The upper 7 bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
ATmega8(L) Table 68.
ATmega8(L) Figure 83. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega8(L) Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 84). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 84. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER Device 3 ........
ATmega8(L) In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared (by writing it to one).
ATmega8(L) Figure 85. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
ATmega8(L) Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated 2. The EEPROM must be instructed what location should be read 3. The reading must be performed 4. The transfer must be finished Note that data is transmitted both from Master to Slave and vice versa.
ATmega8(L) • Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action • Two or more masters are accessing different slaves.
ATmega8(L) Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega8(L) • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
ATmega8(L) Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0(1) pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..
ATmega8(L) Analog-toDigital Converter Features • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13µs - 260µs Conversion Time Up to 15 kSPS at Maximum Resolution 6 Multiplexed Single Ended Input Channels 2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only) Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
ATmega8(L) Figure 90. Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADFR ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX2 MUX1 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 2.
ATmega8(L) If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
ATmega8(L) The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
ATmega8(L) Figure 94. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample &Hold Conversion Complete MUX and REFS Update Table 73. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) Extended conversion 13.5 25 Normal conversions, single ended 1.
ATmega8(L) Changing Channel The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference or Reference selection only takes place at a safe point during the conversion. The channel and reference Selection selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
ATmega8(L) ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled 2.
ATmega8(L) Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks. 2.
ATmega8(L) Figure 97. Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 98.
ATmega8(L) • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB Figure 99. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 100.
ATmega8(L) ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is: V IN 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 74 and Table 75). 0x000 represents ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega8(L) Table 75. Input Channel Selections (Continued) MUX3..0 Single Ended Input 0110 ADC6 0111 ADC7 1000 1001 1010 1011 1100 1101 ADC Control and Status Register A – ADCSRA 1110 1.30V (VBG) 1111 0V (GND) Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC.
ATmega8(L) • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 76.
ATmega8(L) Boot Loader Support – ReadWhile-Write SelfProgramming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega8(L) RWW – Read-WhileWrite Section If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an ongoing programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (that is, by a call/rjmp/lpm or an interrupt) during programming, the software might end up in an unknown state.
ATmega8(L) Figure 102.
ATmega8(L) Table 78. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 Mode BLB01 Mode 1 1 1 No restrictions for SPM or LPM accessing the Application section 2 1 0 SPM is not allowed to write to the Application section 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
ATmega8(L) Table 80. Boot Reset Fuse(1) BOOTRST Note: Store Program Memory Control Register – SPMCR Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see Table 82 on page 213) 1. “1” means unprogrammed, “0” means programmed The Store Program memory Control Register contains the control bits needed to control the Boot Loader operations.
ATmega8(L) • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles.
ATmega8(L) Figure 103. Addressing the Flash during SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: Self-Programming the Flash 1. The different variables used in the figure are listed in Table 84 on page 214 2.
ATmega8(L) Performing Page Erase by SPM To execute page erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
ATmega8(L) See Table 78 on page 205 and Table 79 on page 205 for how the different settings of the Boot Loader Bits affect the Flash access. If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock Bits).
ATmega8(L) Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock Bits to prevent any Boot Loader software updates 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level.
ATmega8(L) Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during self-programming (page erase and page write).
ATmega8(L) ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega8(L) Table 83. Read-While-Write Limit Section Pages Address Read-While-Write section (RWW) 96 0x000 - 0xBFF No Read-While-Write section (NRWW) 32 0xC00 - 0xFFF For details about these two section, see “NRWW – No Read-While-Write Section” on page 203 and “RWW – Read-While-Write Section” on page 203. Table 84.
ATmega8(L) Memory Programming Program And Data Memory Lock Bits The ATmega8 provides six Lock Bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 86. The Lock Bits can only be erased to “1” with the Chip Erase command. Table 85.
ATmega8(L) Table 86. Lock Bit Protection Modes(2) (Continued) Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section 2 1 0 SPM is not allowed to write to the Boot Loader section 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega8(L) Table 88. Fuse Low Byte Fuse Low Byte Bit No.
ATmega8(L) Signature Bytes All Atmel microcontrollers have a 3-byte signature code which identifies the device. This code can be read in both Serial and Parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega8 the signature bytes are: 1. 0x000: 0x1E (indicates manufactured by Atmel) 2. 0x001: 0x93 (indicates 8KB Flash memory) 3.
ATmega8(L) Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock Bits, and Fuse Bits in the ATmega8. Pulses are assumed to be at least 250ns unless otherwise noted. Signal Names In this section, some pins of the ATmega8 are referenced by signal names describing their functionality during parallel programming, see Figure 104 and Table 91.
ATmega8(L) Table 91. Pin Name Mapping (Continued) Signal Name in Programming Mode Pin Name I/O Function PAGEL PD7 I Program memory and EEPROM Data Page Load BS2 PC2 I Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High byte) DATA {PC[1:0]: PB[5:0]} I/O Bi-directional Data bus (Output when OE is low) Table 92. Pin Values used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 93.
ATmega8(L) Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5V - 5.5V between VCC and GND, and wait at least 100µs 2. Set RESET to “0” and toggle XTAL1 at least 6 times 3. Set the Prog_enable pins listed in Table 92 on page 220 to “0000” and wait at least 100ns 4. Apply 11.5V - 12.5V to RESET.
ATmega8(L) Programming the Flash The Flash is organized in pages, see Table 89 on page 218. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading 2. Set BS1 to ”0” 3. Set DATA to “0001 0000”. This is the command for Write Flash 4. Give XTAL1 a positive pulse.
ATmega8(L) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. Set XA1, XA0 to “10”. This enables command loading 2. Set DATA to “0000 0000”. This is the command for No Operation 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset Figure 105.
ATmega8(L) Figure 106. Programming the Flash Waveforms(1) F A DATA 0x10 B ADDR. LOW C DATA LOW D E B C D E DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: Programming the EEPROM 1. “XX” is don’t care. The letters refer to the programming description above The EEPROM is organized in pages, see Table 90 on page 218. When programming the EEPROM, the program data is latched into a page buffer.
ATmega8(L) Figure 107. Programming the EEPROM Waveforms K A DATA 0x11 G ADDR. HIGH B C ADDR. LOW DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 222 for details on Command and Address loading): 1. A: Load Command “0000 0010” 2. G: Load Address High byte (0x00 - 0xFF) 3. B: Load Address Low byte (0x00 - 0xFF) 4.
ATmega8(L) Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 222 for details on Command and Data loading): 1. A: Load Command “0100 0000” 2. C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte 4. Give WR a negative pulse and wait for RDY/BSY to go high 5. Set BS1 to “0”.
ATmega8(L) Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 222 for details on Command and Address loading): 1. A: Load Command “0000 1000” 2. B: Load Address Low byte (0x00 - 0x02) 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4.
ATmega8(L) Figure 111. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) DATA (Low Byte) ADDR1 (Low Byte) DATA (High Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 109 on page 227 (that is, tDVXH, tXHXL, and tXLDX) also apply to reading operation Table 95.
ATmega8(L) Table 95. Parallel Programming Characteristics, VCC = 5V ±10% (Continued) Symbol Parameter tXLOL XTAL1 Low to OE Low 0 tBVDV BS1 Valid to DATA valid 0 tOLDV OE Low to DATA Valid 250 tOHDZ OE High to DATA Tri-stated 250 Notes: Min Typ Max Units 250 ns 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands 2.
ATmega8(L) Serial Downloading Serial Programming Pin Mapping Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 96, the pin mapping for SPI programming is listed.
ATmega8(L) Serial Programming Algorithm When writing serial data to the ATmega8, data is clocked on the rising edge of SCK. When reading data from the ATmega8, data is clocked on the falling edge of SCK. See Figure 113 on page 232 for timing details. To program and verify the ATmega8 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 98 on page 233): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
ATmega8(L) Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
ATmega8(L) Table 98.
ATmega8(L) SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 239.
ATmega8(L) Electrical Characteristics – TA = -40°C to 85°C Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature .....................................
ATmega8(L) TA = -40C to +85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Rpu I/O Pin Pull-up Resistor Condition Min Typ 20 Max Units 50 k Active 4MHz, VCC = 3V (ATmega8L) 3 5 Active 8MHz, VCC = 5V (ATmega8) 11 15 Idle 4MHz, VCC = 3V (ATmega8L) 1 2 Idle 8MHz, VCC = 5V (ATmega8) 4.
ATmega8(L) External Clock Drive Waveforms Figure 114. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 99. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Min Max Min Max Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.5 tCHCX High Time 50 25 tCLCX Low Time 50 25 tCLCH Rise Time 1.6 0.5 tCHCL Fall Time 1.6 0.
ATmega8(L) Two-wire Serial Interface Characteristics Table 101 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 115 on page 239. Table 101. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) Min Max Input Low-voltage -0.5 0.3VCC Input High-voltage 0.
ATmega8(L) 5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement 6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz 7.
ATmega8(L) Figure 116. SPI interface timing requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 117. SPI interface timing requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega8(L) ADC Characteristics Table 103. ADC Characteristics Symbol Min(1) Typ(1) Parameter Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1.
ATmega8(L) Electrical Characteristics – TA = -40°C to 105°C Note: Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature .....................................
ATmega8(L) DC Characteristics TA = -40C to 105C, VCC = 2.7V to 5.
ATmega8(L) ATmega8 Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail-to-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega8(L) Figure 119. Active Supply Current vs. Frequency (1MHz - 20MHz) 30 5.5V 5.0V 25 4.5V ICC (mA) 20 15 10 3.3V 3.0V 5 2.7V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 120. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 18 16 -40°C 25°C 85°C 14 ICC (mA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 121. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 12 10 -40°C 25°C 85°C ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 122. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 6 25°C -40°C 85°C 5 ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 123. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 3.5 3 2.5 ICC (mA) 85°C 25°C -40°C 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 124. Active Supply Current vs. VCC (32kHz External Oscillator) 120 100 25°C ICC (µA) 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Idle Supply Current Figure 125. Idle Supply Current vs. Frequency (0.1MHz - 1.0MHz) 0.7 5.5V ICC (mA) 0.6 5.0V 0.5 4.5V 0.4 4.0V 3.3V 3.0V 2.7V 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) Figure 126. Idle Supply Current vs. Frequency (1MHz - 20MHz) 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 3.0V 2 2.
ATmega8(L) Figure 127. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 8 -40°C 25°C 85°C 7 6 ICC (mA) 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 4 -40°C 25°C 85°C 3.5 3 ICC (mA) 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 129. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz) -40°C 85°C 25°C 1.8 1.6 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 130. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1 85°C 25°C -40°C 0.9 0.8 ICC (mA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 131. Idle Supply Current vs. VCC (32kHz External Oscillator) 40 35 25°C 30 ICC (µA) 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 132. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2.5 85°C 2 1.5 ICC (µA) -40°C 25°C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 133. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 80 85°C 25°C -40°C 70 60 ICC (µA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 134. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 25 25°C 20 ICC (µA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Standby Supply Current Figure 135. Standby Supply Current vs. VCC (455kHz Resonator, Watchdog Timer Disabled) 80 70 60 ICC (µA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 136. Standby Supply Current vs. VCC (1MHz Resonator, Watchdog Timer Disabled) 70 60 ICC (µA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 137. Standby Supply Current vs. VCC (2MHz Resonator, Watchdog Timer Disabled) 90 80 70 ICC (µA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 138. Standby Supply Current vs. VCC (2MHz Xtal, Watchdog Timer Disabled) 90 80 70 ICC (µA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 139. Standby Supply Current vs. VCC (4MHz Resonator, Watchdog Timer Disabled) 140 120 ICC (µA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 140. Standby Supply Current vs. VCC (4MHz Xtal, Watchdog Timer Disabled) 140 120 ICC (µA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 141. Standby Supply Current vs. VCC (6MHz Resonator, Watchdog Timer Disabled) 160 140 120 ICC (µA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 142. Standby Supply Current vs. VCC (6MHz Xtal, Watchdog Timer Disabled) 200 180 160 140 ICC (µA) 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Pin Pull-up Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 85°C 140 25°C 120 -40°C IIO (µA) 100 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) Figure 144. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 85°C 25°C 70 -40°C IIO (µA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega8(L) Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 100 - 40 °C 25°C 80 IRESET (µA) 85°C 60 40 20 0 0 1 2 VRESET (V) Figure 146. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 45 -40°C 40 25°C 35 85°C IRESET (µA) 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Pin Driver Strength Figure 147. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 80 -40°C 70 25°C 60 85°C IOH (mA) 50 40 30 20 10 0 VOH (V) Figure 148. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 30 -40°C 25 25°C 85°C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Figure 149. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 90 80 -40°C 70 25°C IOL (mA) 60 85°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 150. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) 35 -40°C 30 25°C 25 IOL (mA) 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Figure 151. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 5V) 4 3.5 -40°C 3 Current (mA) 25°C 2.5 85°C 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 VOH (V) Figure 152. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 2.7V) 5 4.5 25°C -40°C 4 Current (mA) 3.5 3 2.5 85°C 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Figure 153. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 5V) 14 -40°C 12 25°C Current (mA) 10 85°C 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 154. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 2.7V) 4.5 4 -40°C 3.5 25°C Current (mA) 3 85°C 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Pin Thresholds and Hysteresis Figure 155. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 2.5 -40°C 85°C 25°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 156. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2 -40°C 25°C 85°C Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 157. I/O Pin Input Hysteresis vs. VCC 0.7 85°C -40°C 25°C Input Hysteresis (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 158. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 4 -40°C 85°C 25°C 3.5 Threshold (V) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 159. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 160. Reset Pin as I/O – Pin Hysteresis vs. VCC 2 -40°C 85°C 25°C Input Hysteresis (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 161. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) 2.5 -40°C 25°C 85°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 162. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 163. Reset Input Pin Hysteresis vs. VCC 1 Input Hysteresis (V) 0.8 -40°C 0.6 25°C 0.4 85°C 0.2 0 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Bod Thresholds and Analog Comparator Offset Figure 164. BOD Thresholds vs. Temperature (BOD Level is 4.0V) 4.3 4.2 Rising VCC Threshold (V) 4.1 4 Falling VCC 3.9 3.8 3.
ATmega8(L) Figure 165. BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.8 2.7 Threshold (V) Rising VCC 2.6 Falling VCC 2.5 2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Figure 166. Bandgap Voltage vs. VCC Bandgap Voltage (V) 1.315 1.31 -40°C 1.305 85°C 25°C 1.3 1.295 1.29 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 167. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) 0.003 Comparator Offset Voltage (V) 0.002 0.001 0 -0.001 85°C -0.002 -0.003 25°C -0.004 -0.005 -40°C -0.006 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 168. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) 0.003 Comparator Offset Voltage (V) 0.002 0.001 0 -0.001 85°C -0.002 25°C -0.003 -0.004 -40°C -0.005 0 0.5 1 1.5 2 2.
ATmega8(L) Internal Oscillator Speed Figure 169. Watchdog Oscillator Frequency vs. VCC 1260 -40°C 25°C 1240 85°C 1220 FRC (kHz) 1200 1180 1160 1140 1120 1100 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 170. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.5 5.5V 8.3 8.1 4.0V FRC (MHz) 7.9 7.7 7.5 2.7V 7.3 7.1 6.9 6.7 6.
ATmega8(L) Figure 171. Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.5 -40°C 8.3 25°C 8.1 FRC (MHz) 7.9 85°C 7.7 7.5 7.3 7.1 6.9 6.7 6.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 172. Calibrated 8MHz RC Oscillator Frequency vs.
ATmega8(L) Figure 173. Calibrated 4MHz RC Oscillator Frequency vs. Temperature 4.2 5.5V 4.1 4.0V FRC (MHz) 4 3.9 2.7V 3.8 3.7 3.6 3.5 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 174. Calibrated 4MHz RC Oscillator Frequency vs. VCC 4.2 -40°C 4.1 25°C 4 FRC (MHz) 85°C 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 175. Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value 8 7 FRC (MHz) 6 5 4 3 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 176. Calibrated 2MHz RC Oscillator Frequency vs. Temperature 2.1 5.5V 2.05 4.0V FRC (MHz) 2 1.95 2.7V 1.9 1.85 1.
ATmega8(L) Figure 177. Calibrated 2MHz RC Oscillator Frequency vs. VCC 2.2 2.1 -40°C FRC (MHz) 25°C 2 85°C 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 178. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value 3.8 3.3 FRC (MHz) 2.8 2.3 1.8 1.3 0.
ATmega8(L) Figure 179. Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.04 5.5V 1.02 4.0V FRC (MHz) 1 0.98 2.7V 0.96 0.94 0.92 0.9 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 180. Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.1 1.05 FRC (MHz) -40°C 25°C 1 85°C 0.95 0.9 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 181. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value 1.9 1.7 FRC (MHz) 1.5 1.3 1.1 0.9 0.7 0.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Current Consumption of Peripheral Units Figure 182. Brown-out Detector Current vs. VCC 30 25 -40°C 25°C 85°C ICC (µA) 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 183. ADC Current vs. VCC (AREF = AVCC) 450 400 25°C -40°C 350 85°C ICC (µA) 300 250 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 184. AREF External Reference Current vs. VCC 250 85°C 200 25°C -40°C ICC (µA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 185. 32kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 25 20 25°C ICC (µA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 186. Watchdog Timer Current vs. VCC 80 70 85°C 60 -40°C 25°C ICC (µA) 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 187. Analog Comparator Current vs. VCC 100 85°C 90 25°C 80 -40°C 70 ICC (µA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 188. Programming Current vs. VCC 7 -40°C 6 25°C ICC (mA) 5 85°C 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Current Consumption in Reset and Reset Pulsewidth Figure 189. Reset Supply Current vs. VCC (0.1MHz - 1.0MHz, Excluding Current Through The Reset Pull-up) 4 5.5V 3.5 5.0V 3 4.5V ICC (mA) 2.5 4.0V 2 3.3V 3.0V 2.7V 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 190. Reset Supply Current vs. VCC (1MHz - 20MHz, Excluding Current Through The Reset Pull-up) 25 5.5V 20 5.0V ICC (mA) 4.5V 15 10 3.3V 5 3.0V 2.
ATmega8(L) Figure 191. Reset Pulse Width vs. VCC 1400 1200 Pulsewidth (ns) 1000 800 600 85°C 25°C 400 -40°C 200 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) ATmega8 Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail-to-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega8(L) Figure 0-2. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 12 10 -40°C 25°C 85°C 105°C ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-3. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 6 25°C -40°C 85°C 105°C 5 ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 3.5 3 2.5 ICC (mA) 105°C 25°C 85°C -40°C 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 0-5. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 8 -40°C 25°C 85°C 105°C 7 6 ICC (mA) 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-6. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 4 -40°C 25°C 85°C 105°C 3.5 3 ICC (mA) 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 1.8 105°C -40°C 85°C 25°C 1.6 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1 105°C 85°C 25°C -40°C 0.9 0.8 ICC (mA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 0-9. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 4.5 105°C 4 3.5 ICC (uA) 3 2.5 85°C 2 -40°C 1.5 25°C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-10. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 80 105°C 85°C 25°C -40°C 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 0-11. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
ATmega8(L) Figure 0-12. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 90 80 25°C 85°C 70 -40°C IOP (uA) 60 105°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 0-13. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
ATmega8(L) Figure 0-14. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 45 -40°C 85°C 40 30 IRESET (uA) 25°C 35 105°C 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VRESET (V) Pin Driver Strength Figure 0-15. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs.
ATmega8(L) Figure 0-16. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40°C 25 25°C 20 105°C IOH (mA) 85°C 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 0-17. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 -40°C 80 25°C 70 85°C IOL (mA) 60 105°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega8(L) Figure 0-18. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 -40°C 30 25°C IOL (mA) 25 85°C 105°C 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 0-19. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 4 3.5 -40°C Current (mA) 3 25°C 2.5 85°C 2 105°C 1.5 1 0.5 0 2 2.5 3 3.5 4 4.
ATmega8(L) Figure 0-20. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 5 4.5 25°C 85°C -40°C 4 Current (mA) 3.5 3 2.5 105 °C 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 VOH (V) Figure 0-21. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 14 -40°C 12 25°C Current (mA) 10 85°C 8 105°C 6 4 2 0 0 0.5 1 1.5 2 2.
ATmega8(L) Figure 0-22. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 4.5 4 -40°C 3.5 25°C Current (mA) 3 85°C 2.5 105°C 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 VOL (V) Pin Thresholds and Hysteresis Figure 0-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 -40°C 85°C 105°C 25°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.
ATmega8(L) Figure 0-24. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2 -40°C 25°C 85°C 105°C Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-25. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.7 105°C 85°C -40°C 25°C 0.6 Threshold (V) 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-26. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIH,I/O Pin Read as “1”) RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 4 -40°C 105°C 85°C 25°C 3.5 Threshold (V) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-27. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 105°C 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.
ATmega8(L) Figure 0-28. Reset Pin as I/O – Pin Hysteresis vs. VCC RESET PIN AS I/O - PIN HYSTERESIS vs. VCC 2 -40°C 105°C 85°C 25°C Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-29. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 2.5 -40°C 25°C 85°C 105°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-30. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 105°C 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-31. Reset Input Pin Hysteresis vs. VCC RESET INPUT PIN HYSTERESIS vs. VCC 1 -40°C Threshold (V) 0.8 25°C 0.6 85°C 0.4 105°C 0.2 0 2 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Bod Thresholds and Analog Comparator Offset Figure 0-32. BOD Thresholds vs. Temperature (BOD Level is 4.0V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 4.3 Threshold (V) 4.2 Rising VCC 4.1 4 Falling VCC 3.9 3.8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 110 120 Temperature (˚C) Figure 0-33. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.8 Threshold (V) 2.7 Rising VCC 2.6 Falling VCC 2.
ATmega8(L) Figure 0-34. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC Bandgap Voltage (V) 1.315 1.31 -40°C 105°C 1.305 85°C 25°C 1.3 1.295 1.29 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 0-35. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 0.003 Comparator Offset Voltage (V) 0.002 0.001 0 105°C 85°C -0.001 -0.002 -0.003 25°C -0.004 -0.005 -40°C -0.006 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega8(L) Figure 0-36. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 0.003 Comparator Offset Voltage (V) 0.002 0.001 0 105°C 85°C 25°C -0.001 -0.002 -0.003 -40°C -0.004 -0.005 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Internal Oscillator Speed Figure 0-37. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs.
ATmega8(L) Figure 0-38. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.5 8.3 5.5V 8.1 FRC (MHz) 7.9 4.0V 7.7 7.5 7.3 2.7V 7.1 6.9 6.7 6.5 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) Figure 0-39. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 8.5 -40°C 8.3 25°C FRC (MHz) 8.1 7.9 85°C 7.7 105°C 7.5 7.3 7.1 6.9 6.7 6.5 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-40. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.2 4.1 5.5V 4 FRC (MHz) 4.0V 3.9 3.8 2.7V 3.7 3.6 3.5 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) Figure 0-41. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. VCC 4.2 -40°C 4.1 25°C FRC (MHz) 4 85°C 105°C 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-42. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.1 2.05 5.5V 2 FRC (MHz) 4.0V 1.95 1.9 2.7V 1.85 1.8 1.75 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) Figure 0-43. Calibrated 2 MHz RC Oscillator Frequency vs. VCC CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. VCC 2.2 FRC (MHz) 2.1 -40°C 25°C 85°C 105°C 2 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-44. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.04 1.02 5.5V 1 FRC (MHz) 4.0V 0.98 0.96 2.7V 0.94 0.92 0.9 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) Figure 0-45. Calibrated 1 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. VCC 1.1 FRC (MHz) 1.05 -40°C 25°C 1 85°C 105°C 0.95 0.9 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Current Consumption of Peripheral Units Figure 0-46. Brown-out Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 30 25 -40°C 25°C 85°C 105°C ICC (uA) 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-47. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AVCC 450 -40°C 25°C 85°C 105°C 400 350 ICC (uA) 300 250 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-48. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. V CC 250 85°C -40°C 200 25°C 105°C ICC (uA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-49. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 0.07 -40°C 105°C 85°C 25°C 0.06 ICC (uA) 0.05 0.04 0.03 0.02 0.01 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 0-50. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 120 105°C 100 85°C 25°C -40°C ICC (uA) 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 0-51. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 7 -40°C 6 5 25°C 4 105°C ICC (uA) 85°C 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Current Consumption in Reset and Reset Pulsewidth Figure 0-52. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC 1400 1200 Pulsewidth (ns) 1000 800 105°C 85°C 600 25°C 400 -40°C 200 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG I T H S V N Z C 11 0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 13 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13 0x3C (0x5C) Reserved 0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 49, 67 0x3A (0x5A) GIFR INTF1 INTF0 – – – – – – 67 0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 72, 100, 119 0x38 (0x58) T
ATmega8(L) Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 166 0x00 (0x20) TWBR Notes: Two-wire Serial Interface Bit Rate Register 165 1. Refer to the USART description (“USART” on page 129) for details on how to access UBRRH and UCSRC (“Accessing UBRRH/UCSRC Registers” on page 146) 2. For compatibility with future devices, reserved bits should be written to zero if accessed.
ATmega8(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z, C, N, V, H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z, C, N, V, H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z, C, N, V, S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z, C, N, V, H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z, C, N, V, H 1 SBC Rd, Rr Subtra
ATmega8(L) Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd Rr Rd+1:Rd Rr+1:Rr LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD
ATmega8(L) Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks CLT Clear T in SREG T0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H1 H0 H H 1 1 MCU CONTROL INSTRUCTIONS NOP SLEEP WDR No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr.
ATmega8(L) Ordering Information Speed (MHz) 8 16 8 16 Notes: Ordering Code(2) Package(1) 2.7 - 5.5 ATmega8L-8AU ATmega8L-8AUR(3) ATmega8L-8PU ATmega8L-8MU ATmega8L-8MUR(3) 32A 32A 28P3 32M1-A 32M1-A 4.5 - 5.5 ATmega8-16AU ATmega8-16AUR(3) ATmega8-16PU ATmega8-16MU ATmega8-16MUR(3) 32A 32A 28P3 32M1-A 32M1-A 2.7 - 5.
ATmega8(L) Packaging Information 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
ATmega8(L) 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 A1 B (4 PLACES) 0º ~ 15º REF e E C COMMON DIMENSIONS (Unit of Measure = mm) eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). MIN NOM MAX – – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.
ATmega8(L) 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 5.10 E 4.90 5.00 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig.
ATmega8(L) Errata The revision letter in this section refers to the revision of the ATmega8 device. ATmega8 Rev.
ATmega8(L) 5. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR.
ATmega8(L) Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 1. Updated the datasheet according to the Atmel new Brand Style Guide. 2486Z- 02/11 to 2.Removed the reference to “On-chip debugging” from the content. Rev. 2486AA- 02/2013 3.Added “Electrical Characteristics – TA = -40°C to 105°C” on page 242. 4.
ATmega8(L) Changes from Rev. 1. Updated Table 98 on page 233. 2486S- 08/07 to 2. Updated “Ordering Information” on page 314. Rev. 2486T- 05/08 - Commercial Ordering Code removed. - No Pb-free packaging option removed. Changes from Rev. 1. Updated “Features” on page 1. 2486R- 07/07 to Rev. 2486S- 08/07 2. Added “Data Retention” on page 7. 3. Updated “Errata” on page 318. 4. Updated “Slave Mode” on page 125. Changes from Rev. 1. Added text to Table 81 on page 211. 2486Q- 10/06 to Rev. 2486R- 07/07 2.
ATmega8(L) 8. Updated “Errata” on page 318. Changes from Rev. 1. Removed to instances of “analog ground”. Replaced by “ground”. 2486N-09/04 to 2. Updated Table 7 on page 29, Table 15 on page 38, and Table 100 on page 237. Rev. 2486O-10/04 3. Updated “Calibrated Internal RC Oscillator” on page 30 with the 1MHz default value. 4. Table 89 on page 218 and Table 90 on page 218 moved to new section “Page Size” on page 218. 5.
ATmega8(L) 9. Updated item 4 in the “Serial Programming Algorithm” on page 231. 10. Added tWD_FUSE to Table 97 on page 232 and updated Read Calibration Byte, Byte 3, in Table 98 on page 233. 11. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics – TA = -40°C to 85°C” on page 235. Changes from Rev. 1. Updated VBOT values in Table 15 on page 38. 2486J-02/03 to 2. Updated “ADC Characteristics” on page 241. Rev. 2486K-08/03 3.
ATmega8(L) 16. Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page 209. 17. Added note for RSTDISBL Fuse in Table 87 on page 216. 18. Updated drawings in “Packaging Information” on page 315. Changes from Rev. 1. Added errata for Rev D, E, and F on page 318. 2486H-09/02 to Rev. 2486I-12/02 Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. 2486G-09/02 to Rev. 2486H-09/02 Changes from Rev. 1.
ATmega8(L) Changes from Rev. 1. Updated Typical Start-up Times. 2486C-03/02 to The following tables has been updated: Rev. 2486D-03/02 Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 28, Table 6, “Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 28, Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 29, and Table 12, “Start-up Times for the External Clock Selection,” on page 32. 2.
ATmega8(L) Table of Contents Features 1 Pin Configurations 2 Overview 3 Block Diagram 3 Disclaimer 4 Pin Descriptions 5 Resources 7 Data Retention 7 About Code Examples 8 Atmel AVR CPU Core 9 Introduction 9 Architectural Overview 9 Arithmetic Logic Unit – ALU 11 Status Register 11 General Purpose Register File 12 Stack Pointer 13 Instruction Execution Timing 13 Reset and Interrupt Handling 14 AVR ATmega8 Memories 17 In-System Reprogrammable Flash Program Memory 17 SRAM Data Memory 18 Data Memory Access Ti
ATmega8(L) ADC Noise Reduction Mode 34 Power-down Mode 34 Power-save Mode 34 Standby Mode 35 Minimizing Power Consumption 35 System Control and Reset 37 Internal Voltage Reference 42 Watchdog Timer 43 Timed Sequences for Changing the Configuration of the Watchdog Timer 45 Interrupts 46 Interrupt Vectors in ATmega8 46 I/O Ports 51 Introduction 51 Ports as General Digital I/O 52 Alternate Port Functions 56 Register Description for I/O Ports 65 External Interrupts 66 8-bit Timer/Counter0 69 Overview 69 Tim
ATmega8(L) Timer/Counter Clock Sources 103 Counter Unit 104 Output Compare Unit 105 Compare Match Output Unit 107 Modes of Operation 108 Timer/Counter Timing Diagrams 112 8-bit Timer/Counter Register Description 114 Asynchronous Operation of the Timer/Counter 117 Timer/Counter Prescaler 120 Serial Peripheral Interface – SPI 121 SS Pin Functionality 125 Data Modes 127 USART 129 Overview 129 Clock Generation 130 Frame Formats 133 USART Initialization 134 Data Transmission – The USART Transmitter 136 Data Re
ATmega8(L) ADC Noise Canceler 195 ADC Conversion Result 199 Boot Loader Support – Read-While-Write Self-Programming 202 Boot Loader Features 202 Application and Boot Loader Flash Sections 202 Read-While-Write and No Read-While-Write Flash Sections 202 Boot Loader Lock Bits 204 Entering the Boot Loader Program 205 Addressing the Flash During Self-Programming 207 Self-Programming the Flash 208 Memory Programming 215 Program And Data Memory Lock Bits 215 Fuse Bits 216 Signature Bytes 218 Calibration Byte 218
ATmega8(L) Bod Thresholds and Analog Comparator Offset 298 Internal Oscillator Speed 300 Current Consumption of Peripheral Units 305 Current Consumption in Reset and Reset Pulsewidth 308 Register Summary 309 Instruction Set Summary 311 Ordering Information 314 Packaging Information 315 32A 315 28P3 316 32M1-A 317 Errata 318 ATmega8 Rev. D to I, M 318 Datasheet Revision History 320 Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013 320 Changes from Rev. 2486Y- 10/10 to Rev.
Table of Contents 1 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.
