Datasheet

221
ATmega329/3290/649/6490
2552I–AVR–04/07
Definitions Several terms are used when describing LCD. The definitions in Table 99 are used
throughout this document. 04/07LCD Module Block Diagram
LCD Clock Sources The LCD Controller can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clk
LCD
is by default equal to the system clock, clk
I/O
.
When the LCDCS bit in the LCDCRB Register is written to logic one, the clock source is
taken from the TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC
voltage offset across LCD segments.
LCD Prescaler The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The
LCDPS2:0 bits selects clk
LCD
divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock
further by 1 to 8.
Table 99. Definitions
LCD A passive display panel with terminals leading directly to a segment
Segment The least viewing element (pixel) which can be on or off
Common Denotes how many segments are connected to a segment terminal
Duty 1/(Number of common terminals on a actual LCD display)
Bias 1/(Number of voltage levels used driving a LCD display -1)
Frame Rate Number of times the LCD segments is energized per second.
Clock
Multiplexer
12-bit Prescaler
0
1
Divide by 1 to 8
LCD
Timing
LCDCRB
LCDFRR
clk
i/o
TOSC
LCDCRA
D
A
T
A
B
U
S
clk
LCD
/4096
clk
LCD
/2048
clk
LCD
/128
clk
LCD
/1024
clk
LCD
/512
clk
LCD
/256
clk
LCD
/64
clk
LCD
/16
Analog
Switch
Array
lcdcs
lcdcd2:0
lcdps2:0
clk
LCD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG35
SEG36
SEG37
SEG38
SEG39
COM0
COM1
COM2
COM3
LCD Buffer/
Driver
V
LCD
LCDDR 19 -15
LCDDR 14 -10
LCDDR 9 - 5
LCDDR 4 - 0
LATCH
array
LCD Ouput
Decoder
LCDCCR
lcdcc3:0
Contrast Controller/
Power Supply
clk
LCD_PS
LCD
CAP
40 x
4:1
MUX
LCD_voltage_ok
1/3 V
LCD
1/2 V
LCD
2/3 V
LCD
LCD Display Configuration
lcddc2:0