Datasheet

99
ATmega325/3250/645/6450
2570K–AVR–04/07
16-bit
Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing (event man-
agement), wave generation, and signal timing measurement. The main features are:
•
True 16-bit Design (i.e., Allows 16-bit PWM)
• Two independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Overview Most register and bit references in this section are written in general form. A lower case
“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Com-
pare unit. However, when using the register or bit defines in a program, the precise form
must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 41. For the
actual placement of I/O pins, refer to “Pinout ATmega3250/6450” on page 2. CPU
accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-
specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register
Description” on page 120.
The PRTIM1 bit in “Power Reduction Register” on page 35 must be written to zero to
enable the Timer/Counter1 module.