Datasheet

73
ATmega325/3250/645/6450
2570K–AVR–04/07
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6
.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis-
ter. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP
states that shift out data, the TDO pin drives actively. In other states the pin is pulled
high.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5
.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin can not be used as an I/O
pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4
.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter-
face is enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3:0
Analog to Digital Converter, Channel 3-0.
Table 36. Overriding Signals for Alternate Functions in PF7:PF4
Signal
Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK
PUOE JTAGEN JTAGEN JTAGEN JTAGEN
PUOV1111
DDO E JTAGE N JTAG E N J TAG EN J TAG EN
DDOV 0 SHIFT_IR +
SHIFT_DR
00
PVOE 0 JTAGEN 0 0
PVOV 0 TDO 0 0
PTOE––––
DI EOE J TAGE N JTAG E N J TAG EN J TAG EN
DIEOV0000
DI––––
AIO TDI
ADC7 INPUT
ADC6 INPUT TMS
ADC5 INPUT
TCK
ADC4 INPUT