Datasheet

56
ATmega325/3250/645/6450
2570K–AVR–04/07
EIFR – External Interrupt Flag
Registe
• Bit 7– PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT30..24 pin triggers an interrupt request, PCIF3
becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
This bit is reserved bit in ATmega325/645 and will always be read as zero.
• Bit 6– PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2
becomes set (one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
This bit is reserved bit in ATmega325/645 and will always be read as zero.
• Bit 5– PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 4– PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it. This flag is always cleared when INT0 is configured as a level interrupt.
PCMSK3 – Pin Change Mask
Register 3
(1)
• Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30:24
Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corre-
sponding I/O pin. If PCINT30:24 is set and the PCIE3 bit in EIMSK is set, pin change
interrupt is enabled on the corresponding I/O pin. If PCINT30:24 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
Bit 76543210
0x1C (0x3C) PCIF3 PCIF2 PCIF1 PCIF0
– – – INTF0 EIFR
Read/Write R/W R/W R/W R/W R R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x73)
– PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 PCMSK3
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0