Datasheet

33
ATmega325/3250/645/6450
2570K–AVR–04/07
Power Management
and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR provides various sleep modes allowing the user to tailor the
power consumption to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one
and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR
Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-
save, or Standby) will be activated by the SLEEP instruction. See Table 15 for a sum-
mary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes
up. The MCU is then halted for four cycles in addition to the start-up time, executes the
interrupt routine, and resumes execution from the instruction following SLEEP. The con-
tents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the
Reset Vector.
Figure 12 on page 25 presents the different clock systems in the
ATmega325/3250/645/6450, and their distribution. The figure is helpful in selecting an
appropriate sleep mode.
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains Oscillators Wake-up Sources
Sleep Mode
clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
ASY
Main Clock Source Enabled Timer Osc Enabled INT0 and Pin Change USI Start Condition Timer2 SPM/EEPROM Ready ADC Other I/O
Idle X X X X X
(2)
XXXXXX
ADC Noise
Reduction X X X X
(2)
X
(3)
XX
(2)
XX
Power-down X
(3)
X
Power-save X X
(2)
X
(3)
XX
Standby
(1)
XX
(3)
X