Datasheet

272
ATmega325/3250/645/6450
2570K–AVR–04/07
Parallel Programming
Characteristics
Figure 118. Parallel Programming Timing, Including some General Timing
Requirements
Figure 119. Parallel Programming Timing, Loading Sequence with Timing
Requirements
(1)
Note: 1. The timing requirements shown in Figure 118 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply
to loading operation.
Data & Contol
(DATA, XA0/1, BS1, BS2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)