Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles 32K bytes (ATmega325/ATmega3250) 64K bytes (ATmega645/ATmega6450) – Optional Boot Cod
Features (Continued) • Ultra-Low Power Consumption – Active Mode: 1 MHz, 1.8V: 350 µA 32 kHz, 1.8V: 20 µA (including Oscillator) – Power-down Mode: 100 nA at 1.
ATmega325/3250/645/6450 DNC 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 2.
Overview The ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram PF0 - PF7 VCC DATA DIR. REG. PORTF DATA REGISTER PORTF PC0 - PC7 PA0 - PA7 PORTA DRIVERS PORTF DRIVERS PORTC DRIVERS DATA DIR. REG.
ATmega325/3250/645/6450 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450 The ATmega325, ATmega3250, ATmega645, and ATmega6450 differs only in memory sizes, pin count and pinout. Table 1 on page 6 summarizes the different configurations for the four devices. Table 1.
ATmega325/3250/645/6450 current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 70. Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
AREF This is the analog reference pin for the A/D Converter. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
ATmega325/3250/645/6450 AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4.
the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
ATmega325/3250/645/6450 AVR Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega325/3250/645/6450 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6. Figure 6.
Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
ATmega325/3250/645/6450 moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 246. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATmega325/3250/645/6450 AVR Memories This section describes the different memories in the ATmega325/3250/645/6450. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega325/3250/645/6450 features an EEPROM Memory for data storage. All three memory spaces are linear. In-System Reprogrammable Flash Program Memory The ATmega325/3250/645/6450 contains 32/64K bytes On-chip In-System Reprogrammable Flash memory for program storage.
SRAM Data Memory Figure 10 shows how the ATmega325/3250/645/6450 SRAM Memory is organized. The ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega325/3250/645/6450 Figure 11. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction EEPROM Data Memory Next Instruction The ATmega325/3250/645/6450 contains 1/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
EEARH and EEARL – The EEPROM Address Register Bit 15 14 13 12 11 10 9 8 0x22 (0x42) – – – – – EEAR10 EEAR9 EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 Read/Write Initial Value R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 X X X X X X X X X X X • Bits 15..11 – Res: Reserved Bits These bits are reserved bits in the ATmega325/3250/645/6450 and will always read as zero.
ATmega325/3250/645/6450 The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega325/3250/645/6450 Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
level of the internal BOD does not match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. I/O Memory The I/O space definition of the ATmega325/3250/645/6450 is shown in “Register Summary” on page 328. All ATmega325/3250/645/6450 I/Os and peripherals are placed in the I/O space.
ATmega325/3250/645/6450 System Clock and Clock Options Clock Systems and their Distribution Figure 12 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 33. The clock systems are detailed below. Figure 12.
ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 3.
ATmega325/3250/645/6450 Figure 13. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5. Table 5. Crystal Oscillator Operating Modes CKSEL3:1 Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(1) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.
Notes: Low-frequency Crystal Oscillator 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up.
ATmega325/3250/645/6450 Table 9. Internal Calibrated RC Oscillator Operating Modes(1)(3) Notes: Frequency Range(2) (MHz) CKSEL3..0 7.3 - 8.1 0010 1. The device is shipped with this option selected. 2. The frequency ranges are preliminary values. Actual values are TBD. 3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8.
External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 14. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12. Table 11. Crystal Oscillator Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16 MHz Table 12.
ATmega325/3250/645/6450 Timer/Counter Oscillator ATmega325/3250/645/6450 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when the calibrated internal RC Oscillator is selected as system clock source. The Oscillator is optimized for use with a 32.768 kHz watch crystal. See Figure 13 on page 27 for crystal connection.
frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 13.
ATmega325/3250/645/6450 Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts.
ATmega325/3250/645/6450 Oscillator is stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2. Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode.
Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 44 for details on how to configure the Watchdog Timer. Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.
ATmega325/3250/645/6450 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 15. Table 15.
• Bit 1 - PRUSART: Power Reduction USART Writing logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re-initialized to ensure proper operation. • Bit 0 - PRADC: Power Reduction ADC Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
ATmega325/3250/645/6450 System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 15. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 16. Reset Characteristics Symbol VPOT Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising) TA = -40°C to 85°C 0.7 1.0 1.
ATmega325/3250/645/6450 Figure 16. MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 17. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 16) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
teresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 17. BODLEVEL Fuse Coding(1) BODLEVEL 2..0 Fuses Note: Min VBOT Typ VBOT Max VBOT 11 BOD Disabled 10 1.8 01 2.7 00 4.3 Units V 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test.
ATmega325/3250/645/6450 Figure 20. Watchdog Reset During Operation CC CK MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset.
Internal Voltage Reference ATmega325/3250/645/6450 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 19. To save power, the reference is not always turned on. The reference is on during the following situations: 1.
ATmega325/3250/645/6450 Figure 21. Watchdog Timer WATCHDOG OSCILLATOR WDTCR – Watchdog Timer Control Register Bit 7 6 5 4 3 2 1 0 (0x60) – – – WDCE WDE WDP2 WDP1 WDP0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 WDTCR • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega325/3250/645/6450 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero.
Table 21. Watchdog Timer Prescale Select WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 3.0V Typical Time-out at VCC = 5.0V 0 0 0 16K cycles 17.1 ms 16.3 ms 0 0 1 32K cycles 34.3 ms 32.5 ms 0 1 0 64K cycles 68.5 ms 65 ms 0 1 1 128K cycles 0.14 s 0.13 s 1 0 0 256K cycles 0.27 s 0.26 s 1 0 1 512K cycles 0.55 s 0.52 s 1 1 0 1,024K cycles 1.1 s 1.0 s 1 1 1 2,048K cycles 2.2 s 2.
ATmega325/3250/645/6450 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer.
Interrupts This section describes the specifics of the interrupt handling as performed in ATmega325/3250/645/6450. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 14. Interrupt Vectors in ATmega325/3250/645/6450 Table 22. Reset and Interrupt Vectors Vector No.
ATmega325/3250/645/6450 Table 23 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 23.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments 0x0000 RESET: ldi r16,high(RAMEND); Main program start 0x0001 RAM out SPH,r16 0x0002 ldi r16,low(RAMEND) 0x0003 0x0004 out sei SPL,r16 0x0005 xxx ; Set Stack Pointer to top of ; Enable interrupts ; .
ATmega325/3250/645/6450 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start Moving Interrupts Between Application and Boot Space MCUCR – MCU Control Register 0x382F/0x782F out SPH,r16 ; Set Stack Pointer to top of RAM 0x3830/0x7830 ldi r16,low(RAMEND) 0x3831/0x7831 0x3832/0x7832 out sei SPL,r16 0x3833/0x7833 ; Enable interrupts xxx The MCU Control Register controls the placement of the Interrupt Vector table.
Assembly Code Example Move_interrupts: ;Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<
ATmega325/3250/645/6450 External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles.
EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 (0x69) – – – – – – ISC01 ISC00 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 EICRA • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.
ATmega325/3250/645/6450 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 PCIE3 PCIE2 PCIE1 PCIE0 – – – INT0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x1D (0x3D) EIMSK • Bit 7 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT30..24 pin will cause an interrupt.
EIFR – External Interrupt Flag Registe Bit 7 6 5 4 3 2 1 0 PCIF3 PCIF2 PCIF1 PCIF0 – – – INTF0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x1C (0x3C) EIFR • Bit 7– PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT30..24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
ATmega325/3250/645/6450 PCMSK2 – Pin Change Mask Register 2(1) Bit (0x6D) 7 6 5 4 3 2 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Read/Write Initial Value PCMSK2 • Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23..16 Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega325/3250/645/6450 in “Alternate Port Functions” on page 64. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 24 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 24.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
ATmega325/3250/645/6450 Figure 25.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATmega325/3250/645/6450 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down.
ATmega325/3250/645/6450 Table 26 summarizes the function of the overriding signals. The pin and port indexes from Figure 27 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 26. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 59 for more details about this feature.
ATmega325/3250/645/6450 • OC1A/PCINT13, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt source.
the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 28.
ATmega325/3250/645/6450 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 30. Table 30. Port D Pins Alternate Functions Port Pin Alternate Function PD7 - PD6 - PD5 - PD4 - PD3 - PD2 - PD1 INT0 (External Interrupt0 Input) PD0 ICP1 (Timer/Counter1 Input Capture pin) The alternate pin configuration is as follows: • INT0 – Port D, Bit 1 INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the MCU.
Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 32. Table 32.
ATmega325/3250/645/6450 • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART operates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
Table 34.
ATmega325/3250/645/6450 • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5.
Table 37. Overriding Signals for Alternate Functions in PF3:PF0 Alternate Functions of Port G Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT The alternate pin configuration is as follows: Table 38.
ATmega325/3250/645/6450 Table 39.
Alternate Functions of Port H Port H is only present in ATmega3250/6450. The alternate pin configuration is as follows: Table 40.
ATmega325/3250/645/6450 Table 41 and Table 42 relates the alternate functions of Port H to the overriding signals shown in Figure 27 on page 64. Table 41.
Alternate Functions of Port J Port J is only present in ATmega3250/6450. The alternate pin configuration is as follows: Table 43.
ATmega325/3250/645/6450 Table 44. Overriding Signals for Alternate Functions in PJ7:4 Signal Name PJ6/PCINT30 PJ5/PCINT29 PJ4/PCINT28 PUOE 0 0 0 PUOV 0 0 0 DDOE 0 0 0 DDOV 0 0 0 PVOE 0 0 0 PVOV 0 0 0 PTOE – – – DIEOE PCINT30 • PCIE0 PCINT29 • PCIE0 PCINT28 • PCIE0 DIEOV 0 0 0 DI – – – AIO – – – Table 45.
Register Description for I/O-Ports PORTA – Port A Data Register Bit DDRA – Port A Data Direction Register PINA – Port A Input Pins Address 7 6 5 4 3 2 1 0 0x02 (0x22) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x01 (0x21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0
ATmega325/3250/645/6450 PORTD – Port D Data Register Bit DDRD – Port D Data Direction Register PIND – Port D Input Pins Address 7 6 5 4 3 2 1 0 0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7
PORTG – Port G Data Register DDRG – Port G Data Direction Register PING – Port G Input Pins Address PORTH – Port H Data Register(1) Bit 7 6 5 4 3 2 1 0 0x14 (0x34) – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x13 (0x33) – – – DDG4 DDG3 DDG2 DDG1 DDG0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x12
ATmega325/3250/645/6450 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module.
event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare unit number, in this case unit A. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
ATmega325/3250/645/6450 Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega325/3250/645/6450 Figure 31. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega325/3250/645/6450 to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1).
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 49 on page 94).
ATmega325/3250/645/6450 Figure 34. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
• Timer/Counter Timing Diagrams The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 35 contains timing data for basic Timer/Counter operation.
ATmega325/3250/645/6450 Figure 38 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 38.
Table 47. Waveform Generation Mode Bit Description(1) Mode WGM01 (CTC0) WGM00 (PWM0) Timer/Counter Mode of Operation TOP Update of OCR0A at TOV0 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0A Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
ATmega325/3250/645/6450 Table 50. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 Reserved 1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare match when counting down. 1 1 Set OC0A on compare match when up-counting. Clear OC0A on compare match when counting down. Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set.
OCR0A – Output Compare Register A Bit 7 6 5 0x27 (0x47) 4 3 2 1 0 OCR0A[7:0] OCR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin.
ATmega325/3250/645/6450 Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 40.
ATmega325/3250/645/6450 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • • • • • • • • • • • Overview True 16-bit Design (i.e.
Figure 41. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
ATmega325/3250/645/6450 also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 194.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega325/3250/645/6450 The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega325/3250/645/6450 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 97.
how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 111. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
ATmega325/3250/645/6450 The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L.
Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location.
ATmega325/3250/645/6450 (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously.
Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 45 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega325/3250/645/6450 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 53 on page 120.
Figure 46. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega325/3250/645/6450 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values.
ATmega325/3250/645/6450 OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ( TOP + 1 ) R PCPWM = log ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running.
ATmega325/3250/645/6450 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 49.
non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 1 on page 121). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements.
ATmega325/3250/645/6450 Figure 51. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 52 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 53.
ATmega325/3250/645/6450 Table 54 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 54. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode).
Table 56.
ATmega325/3250/645/6450 (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written.
TCNT1H and TCNT1L – Timer/Counter1 Bit 7 6 5 4 3 (0x85) TCNT1[15:8] (0x84) TCNT1[7:0] 2 1 0 TCNT1H TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
ATmega325/3250/645/6450 TIMSK1 – Timer/Counter1 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6F) – – ICIE1 – – OCIE1B OCIE1A TOIE1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK1 • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled.
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 0 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows.
ATmega325/3250/645/6450 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.
ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC2A). See “Output Compare Unit” on page 129. for details.
ATmega325/3250/645/6450 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped.
The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega325/3250/645/6450 Compare Match Output Unit The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 57 shows a simplified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega325/3250/645/6450 compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 61 on page 139).
ATmega325/3250/645/6450 Figure 60. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
• Timer/Counter Timing Diagrams The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set.
ATmega325/3250/645/6450 Figure 63. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 64 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 64.
8-bit Timer/Counter Register Description TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
ATmega325/3250/645/6450 • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting.
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 63. Table 63. Clock Select Bit Description TCNT2 – Timer/Counter Register CS22 CS21 CS20 0 0 0 No clock source (Timer/Counter stopped).
ATmega325/3250/645/6450 Asynchronous operation of the Timer/Counter ASSR – Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 (0xB6) – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 k
Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2A, and TCCR2A. 4.
ATmega325/3250/645/6450 • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag.
ATmega325/3250/645/6450 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSR2 PSR10 Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware.
SPI – Serial Peripheral Interface The ATmega325/3250/645/6450 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega325/3250/645/6450
ATmega325/3250/645/6450 MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 64. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 64. Table 64. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 148 1.
ATmega325/3250/645/6450 The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega325/3250/645/6450 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 68 and Figure 69 for an example. The CPOL functionality is summarized below: Table 65.
ATmega325/3250/645/6450 SPSR – SPI Status Register Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x2D (0x4D) SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 68 and Figure 69. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 65 and Table 66, as done below: Table 68.
ATmega325/3250/645/6450 USART0 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode.
ATmega325/3250/645/6450 Figure 71. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
Table 69.
ATmega325/3250/645/6450 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 72. Synchronous Mode XCK Timing.
Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame.
ATmega325/3250/645/6450 given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega325/3250/645/6450 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
ATmega325/3250/645/6450 Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done.
The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
ATmega325/3250/645/6450 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e.
ATmega325/3250/645/6450 Figure 74. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
Figure 76. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting.
ATmega325/3250/645/6450 Table 70. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 71.
Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
ATmega325/3250/645/6450 USART Register Description UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
• Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
ATmega325/3250/645/6450 • Bit 3 – TXENn: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD port.
• Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 74. USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 75.
ATmega325/3250/645/6450 • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate.
Table 78. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.
ATmega325/3250/645/6450 Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.
Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.
ATmega325/3250/645/6450 USI – Universal Serial Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load.
selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows.
ATmega325/3250/645/6450 Figure 79. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 79. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register. The second and third instructions clears the USI Counter Overflow Flag and the USI counter value.
ATmega325/3250/645/6450 The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4): SPITransfer_Fast: sts USIDR,r16 ldi r16,(1<
ferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set.
ATmega325/3250/645/6450 Figure 81. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F Referring to the timing diagram (Figure 81.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A).
Start Condition Detector The start condition detector is shown in Figure 82. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
ATmega325/3250/645/6450 (transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges.
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) are can still be used by the counter.
ATmega325/3250/645/6450 USICR – USI Control Register Bit 7 6 5 4 3 2 1 0 USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Read/Write R/W R/W R/W R/W R/W R/W W W Initial Value 0 0 0 0 0 0 0 0 (0xB8) USICR The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. • Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt.
Table 81. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 0 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATmega325/3250/645/6450 • Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..
Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega325/3250/645/6450 • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 84.
ATmega325/3250/645/6450 Analog to Digital Converter Features • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock) Up to 76.9 kSPS at Maximum Resolution (200 kHz ADC clock) Eight Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
Figure 84. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADEN ADSC ADATE 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
ATmega325/3250/645/6450 to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 86. ADC Prescaler ADEN START Reset 7-BIT ADC PRESCALER CK/128 CK/64 CK/32 CK/16 CK/8 CK/4 CK/2 CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution.
ATmega325/3250/645/6450 In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 85. Figure 87.
Figure 90. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update Table 85. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.
ATmega325/3250/645/6450 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 91. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less.
ATmega325/3250/645/6450 Figure 92. ADC Power Connections VCC GND 52 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 10μΗ GND AVCC 100nF Analog Ground Plane ADC Accuracy Definitions 51 63 64 1 DNC PA0 An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 94. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 95.
ATmega325/3250/645/6450 • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 96. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 ADC Conversion Result VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value.
Figure 97. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 86. Correlation Between Input Voltage and Output Codes VADCn Read Code VADCm + VREF 0x1FF 511 VADCm + 511/512 VREF 0x1FF 511 510 0x1FE 510 VADCm + /512 VREF Corresponding Decimal Value ... ... ... VADCm + 1/512 VREF 0x001 1 VADCm 0x000 0 VADCm - /512 VREF 0x3FF -1 ... ... ...
ATmega325/3250/645/6450 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 87.
Table 88. Input Channel Selections MUX4..
ATmega325/3250/645/6450 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value ADLAR = 1 Bit 15 14 13 12 11 10 9 8 (0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH (0x78) ADC1 ADC0 – – – – – – ADCL 7 6 5 4 3 2 1 0 R
ATmega325/3250/645/6450 Table 90.
JTAG Interface and On-chip Debug System Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega325/3250/645/6450 The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP pins are internally pulled high and the JTAG is enabled for Boundaryscan and programming. The device is shipped with this fuse programmed.
Figure 99. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR TAP Controller 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system.
ATmega325/3250/645/6450 state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK.
A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 218. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the Onchip debug system to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door into a secured device.
ATmega325/3250/645/6450 On-chip Debug Related Register in I/O Memory OCDR – On-chip Debug Register Bit 7 6 5 4 3 2 1 0 0x31 (0x51) MSB/IDRD LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
IEEE 1149.1 (JTAG) Boundary-scan Features • • • • • System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register.
ATmega325/3250/645/6450 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register Figure 100 shows the structure of the Device Identification Register. Figure 100.
Figure 101. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 224 for a complete description.
ATmega325/3250/645/6450 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register. The active states are: AVR_RESET; 0xC • Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. • Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
ATmega325/3250/645/6450 Figure 102. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
Figure 103.
ATmega325/3250/645/6450 Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 105 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell.
Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 106. The Boundary-scan cell from Figure 107 is attached to each of these signals. The signals are described in Table 94. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 106. Analog Comparator BANDGAP REFERENCE ACBG ACD ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 107.
ATmega325/3250/645/6450 Table 94.
Table 95.
ATmega325/3250/645/6450 Table 95.
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. 1024 ⋅ 1,5V ⋅ 0,95 ⁄ 5V = 291 = 0x123 1024 ⋅ 1,5V ⋅ 1,05 ⁄ 5V = 323 = 0x143 The lower limit is: The upper limit is: The recommended values from Table 95 are used unless other values are given in the algorithm in Table 96. Only the DAC and port pin values of the Scan Chain are shown.
ATmega325/3250/645/6450 Boundary-scan Order Table 97 and Table 98 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
Table 97. ATmega325/645 Boundary-scan Order, 64-pin (Continued) 234 Bit Number Signal Name 169 MUXEN_4 168 MUXEN_3 167 MUXEN_2 166 MUXEN_1 165 MUXEN_0 164 NEGSEL_2 163 NEGSEL_1 162 NEGSEL_0 161 PASSEN 160 PRECH 159 ST 158 VCCREN 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.
ATmega325/3250/645/6450 Table 97. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name Module 133 PB0.Data Port B 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.
Table 97. ATmega325/645 Boundary-scan Order, 64-pin (Continued) 236 Bit Number Signal Name Module 100 EXTCLKEN Enable signals for main Clock/Oscillators 99 OSCON 98 RCOSCEN 97 OSC32EN 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.Control 78 PD4.
ATmega325/3250/645/6450 Table 97. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 64 PG1.Control 63 PG1.Pull-up_Enable 62 PC0.Data 61 PC0.Control 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.
Table 97. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 28 PA5.Control 27 PA5.Pull-up_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.
ATmega325/3250/645/6450 Table 98.
Table 98. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) 240 Bit Number Signal Name 207 NEGSEL_0 206 PASSEN 205 PRECH 204 ST 203 VCCREN 202 PE0.Data 201 PE0.Control 200 PE0.Pull-up_Enable 199 PE1.Data 198 PE1.Control 197 PE1.Pull-up_Enable 196 PE2.Data 195 PE2.Control 194 PE2.Pull-up_Enable 193 PE3.Data 192 PE3.Control 191 PE3.Pull-up_Enable 190 PE4.Data 189 PE4.Control 188 PE4.Pull-up_Enable 187 PE5.Data 186 PE5.Control 185 PE5.
ATmega325/3250/645/6450 Table 98. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name Module 171 PB0.Control 170 PB0.Pull-up_Enable 169 PB1.Data 168 PB1.Control 167 PB1.Pull-up_Enable 166 PB2.Data 165 PB2.Control 164 PB2.Pull-up_Enable 163 PB3.Data 162 PB3.Control 161 PB3.Pull-up_Enable 160 PB4.Data 159 PB4.Control 158 PB4.Pull-up_Enable 157 PB5.Data 156 PB5.Control 155 PB5.Pull-up_Enable 154 PB6.Data 153 PB6.Control 152 PB6.
Table 98. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) 242 Bit Number Signal Name Module 135 EXTCLK (XTAL1) 134 OSCCK Clock input and Oscillators for the main clock (Observe-only) 133 RCCK 132 OSC32CK 131 PJ2.Data 130 PJ2.Control 129 PJ2.Pull-up_Enable 128 PJ3.Data 127 PJ3.Control 126 PJ3.Pull-up_Enable 125 PJ4.Data 124 PJ4.Control 123 PJ4.Pull-up_Enable 122 PJ5.Data 121 PJ5.Control 120 PJ5.Pull-up_Enable 119 PJ6.Data 118 PJ6.Control 117 PJ6.
ATmega325/3250/645/6450 Table 98. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 99 PD5.Pull-up_Enable 98 PD6.Data 97 PD6.Control 96 PD6.Pull-up_Enable 95 PD7.Data 94 PD7.Control 93 PD7.Pull-up_Enable 92 PG0.Data 91 PG0.Control 90 PG0.Pull-up_Enable 89 PG1.Data 88 PG1.Control 87 PG1.Pull-up_Enable 86 PC0.Data 85 PC0.Control 84 PC0.Pull-up_Enable 83 PC1.Data 82 PC1.Control 81 PC1.Pull-up_Enable 80 PC2.Data 79 PC2.Control 78 PC2.
Table 98. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) 244 Bit Number Signal Name 63 PH1.Pull-up_Enable 62 PH2.Data 61 PH2.Control 60 PH2.Pull-up_Enable 59 PH3.Data 58 PH3.Control 57 PH3.Pull-up_Enable 56 PC6.Data 55 PC6.Control 54 PC6.Pull-up_Enable 53 PC7.Data 52 PC7.Control 51 PC7.Pull-up_Enable 50 PG2.Data 49 PG2.Control 48 PG2.Pull-up_Enable 47 PA7.Data 46 PA7.Control 45 PA7.Pull-up_Enable 44 PA6.Data 43 PA6.Control 42 PA6.
ATmega325/3250/645/6450 Table 98. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 27 PA1.Pull-up_Enable 26 PA0.Data 25 PA0.Control 24 PA0.Pull-up_Enable 23 PH4.Data 22 PH4.Control 21 PH4.Pull-up_Enable 20 PH5.Data 19 PH5.Control 18 PH5.Pull-up_Enable 17 PH6.Data 16 PH6.Control 15 PH6.Pull-up_Enable 14 PH7.Data 13 PH7.Control 12 PH7.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.
Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega325/3250/645/6450 Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
Figure 110.
ATmega325/3250/645/6450 Table 100. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Note: Store Program Memory Control and Status Register – SPMCSR 1. “1” means unprogrammed, “0” means programmed The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega325/3250/645/6450 If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed.
Figure 111. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. The different variables used in Figure 111 are listed in Table 106 on page 258. 2. PCPAGE and PCWORD are listed in Table 116 on page 264.
ATmega325/3250/645/6450 Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. Bit 7 6 5 4 3 2 1 0 R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1 See Table 100 and Table 101 for how the different settings of the Boot Loader bits affect the Flash access. If bits 5..
ATmega325/3250/645/6450 the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 109 on page 260 for detailed description and mapping of the Extended Fuse byte. Bit 7 6 5 4 3 2 1 0 Rd – – – – – EFB2 EFB1 EFB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one.
Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
ATmega325/3250/645/6450 sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega325/3250/645/6450 Boot Loader Parameters In Table 104 through Table 106, the parameters used in the description of the Self-Programming are given. Table 104.
ATmega325/3250/645/6450 Memory Programming Program And Data Memory Lock Bits The ATmega325/3250/645/6450 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 108. The Lock bits can only be erased to “1” with the Chip Erase command. Table 107.
Table 108. Lock Bit Protection Modes(1)(2) (Continued) Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega325/3250/645/6450 Table 110. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode.
ATmega325/3250/645/6450 Figure 112. Parallel Programming +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V BS2 VCC +5V AVCC PB7 - PB0 DATA RESET PA0 XTAL1 GND Table 112. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low).
Table 114. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 115.
ATmega325/3250/645/6450 Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel (High-voltage) Programming mode: 1. Set Prog_enable pins listed in Table 113 on page 263 to “0000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. 3. Ensure that VCC reaches at least 1.8V within the next 20 µs. 4. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 5.
4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. Programming the Flash The Flash is organized in pages, see Table 116 on page 264. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A.
ATmega325/3250/645/6450 H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 114 for signal waveforms). I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse.
Figure 114. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: Programming the EEPROM 1. “XX” is don’t care. The letters refer to the programming description above. The EEPROM is organized in pages, see Table 117 on page 264. When programming the EEPROM, the program data is latched into a page buffer.
ATmega325/3250/645/6450 Figure 115. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 266 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4.
Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 266 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
ATmega325/3250/645/6450 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 266 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4.
Parallel Programming Characteristics Figure 118. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 119.
ATmega325/3250/645/6450 Figure 120. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 118 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 118.
Table 118. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Serial Downloading Serial Programming Pin Mapping Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
ATmega325/3250/645/6450 Serial Programming Algorithm When writing serial data to the ATmega325/3250/645/6450, data is clocked on the rising edge of SCK. When reading data from the ATmega325/3250/645/6450, data is clocked on the falling edge of SCK. See Figure 122 for timing details. To program and verify the ATmega325/3250/645/6450 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 121): 1.
8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 120. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5 ms tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Figure 122.
ATmega325/3250/645/6450 Serial Programming Instruction set Table 121 and Figure 123 on page 278 describes the Instruction set. Table 121.
Notes: 1. 2. 3. 4. Not all instructions are applicable for all parts a = address Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . 5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending.
ATmega325/3250/645/6450 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Figure 124. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR AVR_RESET (0xC) 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
ATmega325/3250/645/6450 PROG_COMMANDS (0x5) PROG_PAGELOAD (0x6) PROG_PAGEREAD (0x7) Data Registers The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register.
Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega325/3250/645/6450 Table 122. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
Table 122. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c.
ATmega325/3250/645/6450 Table 122. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a.
Figure 127.
ATmega325/3250/645/6450 including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 128. Flash Data Byte Register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK.
Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 287. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address High byte using programming instruction 2b. 4. Load address Low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7.
ATmega325/3250/645/6450 ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read.
Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 118 on page 273). Reading the Fuses and Lock Bits 1.
ATmega325/3250/645/6450 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Power Supply Current ICC Power-down mode(5) Condition Max. Units Active 1MHz, VCC = 2V 0.55 mA Active 4MHz, VCC = 3V 2.5 mA Active 8MHz, VCC = 5V 9 mA Idle 1MHz, VCC = 2V 0.2 mA Idle 4MHz, VCC = 3V 0.85 mA Idle 8MHz, VCC = 5V 3 mA Typ. WDT enabled, VCC = 3V 7 15 µA WDT disabled, VCC = 3V 0.
ATmega325/3250/645/6450 External Clock Drive Waveforms Figure 129. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 123. External Clock Drive Speed vs. VCC VCC=1.8-5.5V VCC=2.7-5.5V VCC=4.5-5.5V Symbol Parameter Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator Frequency 0 1 0 8 0 16 MHz tCLCL Clock Period 1000 125 62.5 ns tCHCX High Time 400 50 25 ns tCLCX Low Time 400 50 25 ns tCLCH Rise Time 2.0 1.6 0.5 μs tCHCL Fall Time 2.
Figure 131. Maximum Frequency vs. VCC (8 - 16 MHz). 16 MHz 8 MHz Safe Operating Area 2.7V SPI Timing Characteristics 5.5V See Figure 132 and Figure 133 for details. Table 124. SPI Timing Parameters Description Mode 1 SCK period Master See Table 67 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega325/3250/645/6450 Figure 132. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) MSB ... LSB Figure 133. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ADC Characteristics – Preliminary Data Table 125. ADC Characteristics Symbol Parameter Condition Min Typ Max Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 4.
ATmega325/3250/645/6450 Table 125. ADC Characteristics Symbol Parameter Condition Min Typ Max Units 1.0 1.1 1.2 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Note: 1. Voltage difference between channels Calibrated Internal RC Oscillator Accuracy Table 126. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25°C ±10% User Calibration 7.3 - 8.
Typical Characteristics – Preliminary Data The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
ATmega325/3250/645/6450 Figure 135. Active Supply Current vs. Frequency (1 - 16 MHz)) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 16 MHz 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 6 4.0 V 3.3 V 2.7 V 4 2 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 136. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 14 85°C 25°C -40°C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 137. Active Supply Current vs. V CC (Internal RC Oscillator, CKDIV8 Programmed, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, CKDIV8 PROGRAMMED, 1 MHz 2.5 85°C 2 25°C -40°C ICC (mA) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 138. Active Supply Current vs. VCC (32 kHz External Oscillator) ACTIVE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 70 85 ˚C 60 25 ˚C -40 ˚C I CC (u A) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Idle Supply Current Figure 139. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.4 5.5 V 0.35 5.0 V 0.3 4.5 V ICC (mA) 0.25 4.0 V 0.2 3.3 V 0.15 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 140. Idle Supply Current vs. Frequency (1 - 16 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 16 MHz 6 5.5 V 5 5.0 V 4.5 V ICC (mA) 4 3 2 4.0 V 3.3 V 1 2.7 V 1.
Figure 141. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 7 6 85°C 5 -40°C ICC (mA) 25°C 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 142. Idle Supply Current vs. VCC (Internal RC Oscillator, CKDIV8 Programmed, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, CKDIV8 PROGRAMMED, 1 MHz 1 0.9 85°C 0.8 25°C 0.7 -40°C ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 143. Idle Supply Current vs. VCC (32 kHz External Oscillator) IDLE SUPPLY CURRENT vs. V CC 32kHz EXTERNAL OSCILLATOR 35 85 ˚C 30 25 ˚C -40 ˚C ICC (uA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
Example Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. Table 128 shows that we need to add 8.5% for the USART0, 9% for the SPI, and 4.8% for the TIMER1 module. From Figure 139, we find that the idle current consumption is ~0.16mA at VCC = 3.0V and F = 1MHz.
ATmega325/3250/645/6450 Power-save Supply Current Figure 146. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 30 25 85°C 25°C ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 147. Standby Supply Current vs. VCC (Low Power Crystal Oscillator) STANDBY SUPPLY CURRENT vs. VCC Low Power Crystal Oscillator 180 6 MHz Xtal 6 MHz Res. 160 140 4 MHz Res.
Pin Pull-up Figure 148. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 85°C 140 25°C 120 -40°C IIO (uA) 100 80 60 40 20 0 0 1 2 3 4 5 VIO (V) Figure 149. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 90 80 25°C 85°C 70 -40°C IIO (uA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega325/3250/645/6450 Figure 150. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 1.8V 60 50 85°C 25°C IOP (uA) 40 -40°C 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 151. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
Figure 152. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 70 60 -40°C 25°C IRESET (uA) 50 85°C 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 153. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 1.8V 40 -40°C 35 25°C 30 IRESET (uA) 85°C 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega325/3250/645/6450 Pin Driver Strength Figure 154. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G, H, J Vcc = 5V 70 IOH (mA) 60 -40°C 50 25°C 40 85°C 30 20 10 0 0 1 2 3 4 5 6 VOH (V) Figure 155. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G, H, J Vcc = 2.
Figure 156. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G, H, J Vcc = 1.8V 8 -40°C 7 25°C 6 85°C IOH (mA) 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Figure 157. I/O Pin Source Current vs. Output Voltage, Port B (VCC= 5V) I/O PIN SOURCE CURRENT vs.
ATmega325/3250/645/6450 Figure 158. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B Vcc = 2.7V 35 30 -40°C 25°C 25 IOH (mA) 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 159. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B Vcc = 1.8V 10 -40°C 9 25°C 8 85°C IOH (mA) 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 160. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G, H, J Vcc = 5V 50 -40°C 45 40 25°C IOL (mA) 35 85°C 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 161. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G, H, J Vcc = 2.
ATmega325/3250/645/6450 Figure 162. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G, H, J Vcc = 1.8V 7 -40°C 6 25°C IOL (mA) 5 85°C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 163. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B Vcc = 5V 90 80 -40°C 70 25°C IOL (mA) 60 85°C 50 40 30 20 10 0 0 0.2 0.4 0.
Figure 164. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B Vcc = 2.7V 35 -40°C 30 25°C 25 IOL (mA) 85°C 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 165. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B Vcc = 1.8V 12 -40°C 10 25°C 85°C IOL (mA) 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega325/3250/645/6450 Pin Thresholds and hysteresis Figure 166. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, I/O PIN READ AS '1' 3 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 167. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, I/O PIN READ AS '0' 3 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.
Figure 168. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.6 -40°C 0.5 Input Hysteresis (V) 25°C 0.4 85°C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 169. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 2.5 Threshold (V) 2 1.5 -40°C 25°C 1 85°C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 170. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 5 5.5 VCC (V) Figure 171. Reset Input Pin Hysteresis vs. VCC RESET INPUT PIN HYSTERESIS vs. VCC 0.7 0.6 -40°C Input Hysteresis (V) 0.5 25°C 0.4 0.3 85°C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.
BOD Thresholds and Analog Comparator Offset Figure 172. BOD Thresholds vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.6 4.5 Rising VCC Threshold (V) 4.4 4.3 Falling VCC 4.2 4.1 4 -60 -40 -20 0 20 40 60 80 100 80 100 Temperature (C) Figure 173. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 3 2.9 Rising VCC Threshol d ( V) 2.8 2.7 Falling VCC 2.6 2.5 2.
ATmega325/3250/645/6450 Figure 174. BOD Thresholds vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V 1.95 Threshold (V) 1.9 Rising VCC 1.85 1.8 Falling VCC 1.75 1.7 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 175. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC 1.076 1.075 Bandgap Voltage (V) 1.074 25˚C 1.073 1.072 85˚C 1.071 1.07 1.069 -40˚C 1.068 1.5 2 2.5 3 3.5 4 4.
Figure 176. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5 V 0.007 85˚C Comparator Offset Voltage (V) 0.006 0.005 25˚C 0.004 0.003 -40˚C 0.002 0.001 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 177. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7 V 0.0035 Comparator Offset Voltage (V) 0.003 0.
ATmega325/3250/645/6450 Internal Oscillator Speed Figure 178. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs.VCC 1300 1250 -40 ˚C 25 ˚C 85 ˚C F RC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 179. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.6 8.4 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V F RC (M Hz) 8.2 8 7.8 7.6 7.4 7.
Figure 180. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 8.6 8.4 85 ˚C 8.2 F RC (MHz) 25 ˚C 8 -40 ˚C 7.8 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 181. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs.
ATmega325/3250/645/6450 Current Consumption of Peripheral Units Figure 182. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 40 -40 ˚C 25 ˚C 85 ˚C 35 30 I CC (u A) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 183. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AVCC 350 -40°C 25°C 85°C 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 184. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. V CC 85°C 25°C -40°C 160 140 120 IAREF (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 185. 32 kHZ TOSC Current vs. VCC (Watchdog Timer Disabled) 32kHz TOSC CURRENT vs. VCC WATCHDOG TIMER DISABLED 25 85°C 25°C 20 ICC (uA) 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 186. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 16 85°C 25°C -40°C 14 12 ICC (uA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 187. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 120 100 -40°C 80 25°C ICC (uA) 85°C 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 188. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 20 -40 ˚C 18 ICC (mA) 16 14 25 ˚C 12 85 ˚C 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 189. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.2 0.18 5.5 V 0.16 5.0 V 0.14 4.5 V ICC (mA) 0.12 4.0 V 0.1 3.3 V 0.08 0.06 2.
ATmega325/3250/645/6450 Figure 190. Reset Supply Current vs. VCC (1 - 16 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. V CC 1 - 16 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 3 5.5 V 2.5 5.0 V ICC (mA) 2 4.5 V 1.5 1 4.0 V 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 191. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 500 85°C 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Register Summary Note: Registers with bold type only available in ATmega3250/6450.
ATmega325/3250/645/6450 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 175 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 174 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 173 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserved - - - - - - - - (0xBB) Reserve
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x83) Reserved - - - - - - - - Page (0x82) TCCR1C FOC1A FOC1B - - - - - - 123 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 122 120 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 196 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 213 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0
ATmega325/3250/645/6450 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 93 0x23 (0x43) GTCCR TSM - - - - - PSR2 PSR10 98/145 0x22 (0x42) EEARH - - - - - 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR - - - - EERIE EEPROM Address Register High Page 20 20 20 EEMWE EEWE EERE General Purpose I/O Register 20 0x1E (0x3E) G
Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd
ATmega325/3250/645/6450 Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+
Mnemonics POP Operands Rd Description Pop Register from Stack Operation Rd ← STACK Flags #Clocks None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega325/3250/645/6450 Ordering Information ATmega325 Speed (MHz)(3) 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega325V-8AI ATmega325V-8AU(2) ATmega325V-8MI ATmega325V-8MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega325-16AI ATmega325-16AU(2) ATmega325-16MI ATmega325-16MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) Power Supply Operational Range 1. This device can also be supplied in wafer form.
ATmega3250 Speed (MHz)(3) Power Supply 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega3250V-8AI ATmega3250V-8AU(2) 100A 100A Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega3250-16AI ATmega3250-16AU(2) 100A 100A Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega325/3250/645/6450 ATmega645 Speed (MHz)(3) 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega645V-8AI ATmega645V-8AU(2) ATmega645V-8MI ATmega645V-8MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega645-16AI ATmega645-16AU(2) ATmega645-16MI ATmega645-16MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) Power Supply Operational Range 1. This device can also be supplied in wafer form.
ATmega6450 Speed (MHz)(3) Power Supply 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega6450V-8AI ATmega6450V-8AU(2) 100A 100A Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega6450-16AI ATmega6450-16AU(2) 100A 100A Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega325/3250/645/6450 Packaging Information 64A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.
64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 – 0.02 0.05 0.18 0.25 0.30 A1 b K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. D 8.90 9.00 9.10 D2 5.
ATmega325/3250/645/6450 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.
Errata ATmega325 Rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
ATmega325/3250/645/6450 ATmega3250 Rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. Rev. 2570K – 04/07 1. Updated Errata on page 342. 1. 2. Updated Table 125 on page 296. Updated note in Table 125 on page 296. 1. 2. 3. 4. 5. 6. Updated Table 33 on page 89.
ATmega325/3250/645/6450 Rev. 2570D – 05/05 1. 2. 3. 4. 5. 6. 7. 8. 9. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”. Added “Pin Change Interrupt Timing” on page 53. Updated “Signature Bytes” on page 262. Updated Table 121 on page 277. Added Figure 123 on page 278. Updated Figure 92 on page 205 and Figure 116 on page 270. Updated algorithm “Enter Programming Mode” on page 265. Added “Supply Current of I/O modules” on page 303.
ATmega325/3250/645/6450 2570K–AVR–04/07
ATmega325/3250/645/6450 Table of Contents Features................................................................................................ 1 Features (Continued)........................................................................... 2 Pin Configurations............................................................................... 2 Disclaimer ............................................................................................................. 3 Overview................................
Idle Mode ............................................................................................................ ADC Noise Reduction Mode............................................................................... Power-down Mode.............................................................................................. Power-save Mode............................................................................................... Standby Mode........................................................
ATmega325/3250/645/6450 Modes of Operation .......................................................................................... 111 Timer/Counter Timing Diagrams....................................................................... 118 16-bit Timer/Counter Register Description ....................................................... 120 8-bit Timer/Counter2 with PWM and Asynchronous Operation .. 127 Overview..............................................................................................
Prescaling and Conversion Timing ................................................................... Changing Channel or Reference Selection ...................................................... ADC Noise Canceler......................................................................................... ADC Conversion Result.................................................................................... 200 202 203 207 JTAG Interface and On-chip Debug System .................................
ATmega325/3250/645/6450 Absolute Maximum Ratings*............................................................................. 291 DC Characteristics............................................................................................ 291 External Clock Drive Waveforms ...................................................................... 293 External Clock Drive ......................................................................................... 293 Speed vs. VCC ...............................
Rev. 2570A – 09/04 .......................................................................................... 345 Table of Contents .................................................................................
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