Datasheet

84
8011Q–AVR–02/2013
ATmega164P/324P/644P
• T0/XCK0/PCINT8, Bit 0
T0, Timer/Counter0 counter source.
XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock
is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the
USART0 operates in Synchronous mode.
PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
Table 11-7 and Table 11-8 relate the alternate functions of Port B to the overriding signals
shown in Figure 11-5 on page 78. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. .
Table 11-7. Overriding Signals for Alternate Functions in PB7:PB4
Signal
Name
PB7/SCK/
PCINT15
PB6/MISO/
PCINT14
PB5/MOSI/
PCINT13
PB4/SS/OC0B/
PCINT12
PUOE SPE • MSTR
SPE • MSTR SPE • MSTR SPE • MSTR
PUOV PORTB7 • PUD PORTB14 • PUD PORTB13 • PUD PORTB12 • PUD
DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
DDOV 0 0 0 0
PVOE SPE • MSTR SPE • MSTR
SPE • MSTR OC0A ENABLE
PVOV SCK OUTPUT
SPI SLAVE
OUTPUT
SPI MSTR OUTPUT OC0A
DIEOE PCINT15 • PCIE1 PCINT14 • PCIE1 PCINT13 • PCIE1 PCINT12 • PCIE1
DIEOV1111
DI
SCK INPUT
PCINT17 INPUT
SPI MSTR INPUT
PCINT14 INPUT
SPI SLAVE INPUT
PCINT13 INPUT
SPI SS
PCINT12 INPUT
AIO––––
Table 11-8. Overriding Signals for Alternate Functions in PB3:PB0
Signal
Name
PB3/AIN1/OC0B/
PCINT11
PB2/AIN0/INT2/
PCINT10
PB1/T1/CLKO/PCIN
T9
PB0/T0/XCK/
PCINT8
PUOE0000
PUOV0000
DDOE 0 0 CKOUT 0
DDOV 0 0 CKOUT 0
PVOE OC0B ENABLE 0 CKOUT 0
PVOV OC0B 0 CLK I/O 0
DIEOE PCINT11 • PCIE1
INT2 ENABLE
PCINT10 • PCIE1
PCINT9 • PCIE1 PCINT8 • PCIE1
DIEOV 1 1 1 1
DI PCINT11 INPUT
INT2 INPUT
PCINT10 INPUT
T1 INPUT
PCINT9 INPUT
T0 INPUT
PCINT8 INPUT
AIO AIN1 INPUT AIN0 INPUT – –