Datasheet

8011Q–AVR–02/2013

ATmega164P/324P/644P

7.12 Register Description

7.12.1 SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 7-2.

Note: 1. Standby modes are only recommended for use with external crystals or resonators.

• Bit 0 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

Bit 76543210

0x33 (0x53) ––––SM2SM1SM0SESMCR

Read/Write RRRRR/WR/WR/WR/W

Initial Value00000000

Table 7-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle

0 0 1 ADC Noise Reduction

010Power-down

011Power-save

100Reserved

101Reserved

110Standby

(1)

1 1 1 Extended Standby

(1)