Datasheet

174
8011Q–AVR–02/2013
ATmega164P/324P/644P
f
OSC
System Oscillator clock frequency
UBRRn Contents of the UBRRHn and UBRRLn Registers, (0-4095)
Some examples of UBRRn values for some system clock frequencies are found in Table 16-9 on
page 194.
16.4.2 Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
16.4.3 External Clock
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to Figure 16-2 on page 173 for details.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
Table 16-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating Baud
Rate
(1)
Equation for Calculating UBRR
Value
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
BAUD
f
OSC
16 UBRRn 1+
------------------------------------------=
UBRRn
f
OSC
16BAUD
------------------------ 1–=
BAUD
f
OSC
8 UBRRn 1+
---------------------------------------=
UBRRn
f
OSC
8BAUD
-------------------- 1–=
BAUD
f
OSC
2 UBRRn 1+
---------------------------------------=
UBRRn
f
OSC
2BAUD
-------------------- 1–=