Datasheet

v
8272A–AVR–01/10
164A/164PA/324A/324PA/644A/644PA/1284/1284P
20.22-wire Serial Interface Bus Definition ..................................................................208
20.3Data Transfer and Frame Format ........................................................................209
20.4Multi-master Bus Systems, Arbitration and Synchronization ...............................212
20.5Overview of the TWI Module ...............................................................................214
20.6Using the TWI ......................................................................................................216
20.7Transmission Modes ...........................................................................................219
20.8Multi-master Systems and Arbitration ..................................................................232
20.9Register Description ............................................................................................233
21 AC - Analog Comparator ..................................................................... 238
21.1Overview .............................................................................................................238
21.2Analog Comparator Multiplexed Input .................................................................238
21.3Register Description ............................................................................................239
22 ADC - Analog-to-digital Converter ..................................................... 241
22.1Features ..............................................................................................................241
22.2Overview .............................................................................................................241
22.3Operation .............................................................................................................242
22.4Starting a Conversion ..........................................................................................243
22.5Prescaling and Conversion Timing ......................................................................244
22.6Changing Channel or Reference Selection .........................................................247
22.7ADC Noise Canceler ...........................................................................................249
22.8ADC Conversion Result ......................................................................................254
22.9Register Description ............................................................................................256
23 JTAG Interface and On-chip Debug System ..................................... 261
23.1Features ..............................................................................................................261
23.2Overview .............................................................................................................261
23.3TAP – Test Access Port ......................................................................................261
23.4TAP Controller .....................................................................................................263
23.5Using the Boundary-scan Chain ..........................................................................264
23.6Using the On-chip Debug System .......................................................................264
23.7On-chip Debug Specific JTAG Instructions .........................................................265
23.8Using the JTAG Programming Capabilities .........................................................265
23.9Bibliography .........................................................................................................266
23.10Register Description ..........................................................................................266
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 267
24.1Features ..............................................................................................................267