Datasheet

299
8272A–AVR–01/10
164A/164PA/324A/324PA/644A/644PA/1284/1284P
26.6 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in
the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. Pulses are assumed to be at
least 250 ns unless otherwise noted.
26.6.1 Signal Names
In this section, some pins of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
are referenced by signal names describing their functionality during parallel programming, see
Figure 26-1 on page 299 and Figure 26-9 on page 300. Pins not described in the following table
are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in Table 26-12 on page 300.
When pulsing WR
or OE, the command loaded determines the action executed. The different
commands are shown in Table 26-13 on page 301.
Figure 26-1. Parallel Programming
(1)
Note: 1. Unused Pins should be left floating.
Table 26-8. No. of Words in a Page and No. of Pages in the EEPROM
Device EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB
ATmega164A/ATmega164PA 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
ATmega324A/ATmega324PA 1 Kbytes 4 bytes EEA[1:0] 256 EEA[9:2] 9
ATmega644A/ATmega644PA 2 Kbytes 8 bytes EEA[2:0] 256 EEA[10:2] 10
ATmega1284/ATmega1284P 4 Kbytes 8 bytes EEA[2:0] 512 EEA[11:3] 11
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PB7 - PB0 DATA
RESET
PD7
+12 V
BS1
XA0
XA1
OE
RDY/BSY
PAGEL
PA0
WR
BS2
AVCC
+5V