Datasheet

162
8272A–AVR–01/10
164A/164PA/324A/324PA/644A/644PA/1284/1284P
17. SPI – Serial Peripheral Interface
17.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
17.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and peripheral devices or between
several AVR devices.
USART can also be used in Master SPI mode, see ”USART in SPI Mode” on page 199.
The Power Reduction SPI bit, PRSPI, in ”PRR – Power Reduction Register” on page 49 on page
50 must be written to zero to enable SPI module.