Datasheet

15
8272A–AVR–01/10
164A/164PA/324A/324PA/644A/644PA/1284/1284P
6.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low
Note: 1. Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
6.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
CPU
, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6-4 on page 15 shows the parallel instruction fetches and instruction executions enabled
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 6-4. The Parallel Instruction Fetches and Instruction Executions
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit 151413121110 9 8
0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R R R R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0/0
(1)
0/1
(1)
1/0
(1)
00
11111111
Table 6-2. Stack Pointer size
Device Stack Pointer size
ATmega164A/ATmega164PA SP[10:0]
ATmega324A/ATmega324PA SP[11:0]
ATmega644A/ATmega644PA SP[12:0]
ATmega1284/ATmega1284P SP[13:0]
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU